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Evandro Menezes
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[AArch64] Refactor Exynos machine model (NFC)
llvm-svn: 345187
1 parent 80bc136 commit 769d4ce

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4 files changed

+42
-42
lines changed

4 files changed

+42
-42
lines changed

‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -696,7 +696,7 @@ bool AArch64InstrInfo::isAsCheapAsAMove(const MachineInstr &MI) const {
696696
// Secondly, check cases specific to sub-targets.
697697

698698
if (Subtarget.hasExynosCheapAsMoveHandling()) {
699-
if (isExynosResetFast(MI) || isExynosShiftLeftFast(MI))
699+
if (isExynosResetFast(MI) || isExynosShiftExtFast(MI))
700700
return true;
701701
else
702702
return MI.isAsCheapAsAMove();
@@ -821,7 +821,7 @@ bool AArch64InstrInfo::isExynosResetFast(const MachineInstr &MI) const {
821821
}
822822
}
823823

824-
bool AArch64InstrInfo::isExynosShiftLeftFast(const MachineInstr &MI) const {
824+
bool AArch64InstrInfo::isExynosShiftExtFast(const MachineInstr &MI) const {
825825
unsigned Imm, Shift;
826826
AArch64_AM::ShiftExtendType Ext;
827827

‎llvm/lib/Target/AArch64/AArch64InstrInfo.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -255,7 +255,7 @@ class AArch64InstrInfo final : public AArch64GenInstrInfo {
255255
bool isExynosResetFast(const MachineInstr &MI) const;
256256
/// Returns true if the instruction has a shift left that can be executed
257257
/// more efficiently.
258-
bool isExynosShiftLeftFast(const MachineInstr &MI) const;
258+
bool isExynosShiftExtFast(const MachineInstr &MI) const;
259259
/// Returns true if the instruction has a shift by immediate that can be
260260
/// executed in one cycle less.
261261
bool isFalkorShiftExtFast(const MachineInstr &MI) const;

‎llvm/lib/Target/AArch64/AArch64SchedExynosM1.td

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -64,9 +64,9 @@ def M1UnitNALU : ProcResGroup<[M1UnitNAL0,
6464
//===----------------------------------------------------------------------===//
6565
// Predicates.
6666

67-
def M1BranchLinkFastPred : SchedPredicate<[{MI->getOpcode() == AArch64::BLR &&
68-
MI->getOperand(0).getReg() != AArch64::LR}]>;
69-
def M1ShiftLeftFastPred : SchedPredicate<[{TII->isExynosShiftLeftFast(*MI)}]>;
67+
def M1BranchLinkPred : SchedPredicate<[{MI->getOpcode() == AArch64::BLR &&
68+
MI->getOperand(0).getReg() != AArch64::LR}]>;
69+
def M1ShiftExtPred : SchedPredicate<[{TII->isExynosShiftExtFast(*MI)}]>;
7070

7171
//===----------------------------------------------------------------------===//
7272
// Coarse scheduling model.
@@ -85,14 +85,14 @@ def M1WriteAC : SchedWriteRes<[M1UnitALU,
8585
def M1WriteAD : SchedWriteRes<[M1UnitALU,
8686
M1UnitC]> { let Latency = 2;
8787
let NumMicroOps = 2; }
88-
def M1WriteAX : SchedWriteVariant<[SchedVar<M1ShiftLeftFastPred, [M1WriteA1]>,
89-
SchedVar<NoSchedPred, [M1WriteAA]>]>;
88+
def M1WriteAX : SchedWriteVariant<[SchedVar<M1ShiftExtPred, [M1WriteA1]>,
89+
SchedVar<NoSchedPred, [M1WriteAA]>]>;
9090
def M1WriteC1 : SchedWriteRes<[M1UnitC]> { let Latency = 1; }
9191
def M1WriteC2 : SchedWriteRes<[M1UnitC]> { let Latency = 2; }
9292

9393
def M1WriteB1 : SchedWriteRes<[M1UnitB]> { let Latency = 1; }
94-
def M1WriteBX : SchedWriteVariant<[SchedVar<M1BranchLinkFastPred, [M1WriteAB]>,
95-
SchedVar<NoSchedPred, [M1WriteAC]>]>;
94+
def M1WriteBX : SchedWriteVariant<[SchedVar<M1BranchLinkPred, [M1WriteAB]>,
95+
SchedVar<NoSchedPred, [M1WriteAC]>]>;
9696

9797
def M1WriteL5 : SchedWriteRes<[M1UnitL]> { let Latency = 5; }
9898
def M1WriteL6 : SchedWriteRes<[M1UnitL]> { let Latency = 6; }
@@ -110,10 +110,10 @@ def M1WriteLD : SchedWriteRes<[M1UnitL,
110110
let ResourceCycles = [2, 1]; }
111111
def M1WriteLH : SchedWriteRes<[]> { let Latency = 5;
112112
let NumMicroOps = 0; }
113-
def M1WriteLX : SchedWriteVariant<[SchedVar<M1ShiftLeftFastPred, [M1WriteL5]>,
114-
SchedVar<NoSchedPred, [M1WriteLC]>]>;
115-
def M1WriteLY : SchedWriteVariant<[SchedVar<M1ShiftLeftFastPred, [M1WriteL5]>,
116-
SchedVar<NoSchedPred, [M1WriteLD]>]>;
113+
def M1WriteLX : SchedWriteVariant<[SchedVar<M1ShiftExtPred, [M1WriteL5]>,
114+
SchedVar<NoSchedPred, [M1WriteLC]>]>;
115+
def M1WriteLY : SchedWriteVariant<[SchedVar<M1ShiftExtPred, [M1WriteL5]>,
116+
SchedVar<NoSchedPred, [M1WriteLD]>]>;
117117

118118
def M1WriteS1 : SchedWriteRes<[M1UnitS]> { let Latency = 1; }
119119
def M1WriteS3 : SchedWriteRes<[M1UnitS]> { let Latency = 3; }
@@ -140,10 +140,10 @@ def M1WriteSD : SchedWriteRes<[M1UnitS,
140140
def M1WriteSE : SchedWriteRes<[M1UnitS,
141141
M1UnitA]> { let Latency = 2;
142142
let NumMicroOps = 2; }
143-
def M1WriteSX : SchedWriteVariant<[SchedVar<M1ShiftLeftFastPred, [M1WriteS1]>,
144-
SchedVar<NoSchedPred, [M1WriteSE]>]>;
145-
def M1WriteSY : SchedWriteVariant<[SchedVar<M1ShiftLeftFastPred, [M1WriteS1]>,
146-
SchedVar<NoSchedPred, [M1WriteSB]>]>;
143+
def M1WriteSX : SchedWriteVariant<[SchedVar<M1ShiftExtPred, [M1WriteS1]>,
144+
SchedVar<NoSchedPred, [M1WriteSE]>]>;
145+
def M1WriteSY : SchedWriteVariant<[SchedVar<M1ShiftExtPred, [M1WriteS1]>,
146+
SchedVar<NoSchedPred, [M1WriteSB]>]>;
147147

148148
def M1ReadAdrBase : SchedReadVariant<[SchedVar<ScaledIdxPred, [ReadDefault]>,
149149
SchedVar<NoSchedPred, [ReadDefault]>]>;

‎llvm/lib/Target/AArch64/AArch64SchedExynosM3.td

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -106,15 +106,15 @@ def M3UnitNSHF : ProcResGroup<[M3UnitNSHF0,
106106
//===----------------------------------------------------------------------===//
107107
// Predicates.
108108

109-
def M3BranchLinkFastPred : SchedPredicate<[{MI->getOpcode() == AArch64::BLR &&
110-
MI->getOperand(0).isReg() &&
111-
MI->getOperand(0).getReg() != AArch64::LR}]>;
112-
def M3ResetFastPred : SchedPredicate<[{TII->isExynosResetFast(*MI)}]>;
113-
def M3RotateRightFastPred : SchedPredicate<[{(MI->getOpcode() == AArch64::EXTRWrri ||
114-
MI->getOpcode() == AArch64::EXTRXrri) &&
115-
MI->getOperand(1).isReg() && MI->getOperand(2).isReg() &&
116-
MI->getOperand(1).getReg() == MI->getOperand(2).getReg()}]>;
117-
def M3ShiftLeftFastPred : SchedPredicate<[{TII->isExynosShiftLeftFast(*MI)}]>;
109+
def M3BranchLinkPred : SchedPredicate<[{MI->getOpcode() == AArch64::BLR &&
110+
MI->getOperand(0).isReg() &&
111+
MI->getOperand(0).getReg() != AArch64::LR}]>;
112+
def M3ResetPred : SchedPredicate<[{TII->isExynosResetFast(*MI)}]>;
113+
def M3RotatePred : SchedPredicate<[{(MI->getOpcode() == AArch64::EXTRWrri ||
114+
MI->getOpcode() == AArch64::EXTRXrri) &&
115+
MI->getOperand(1).isReg() && MI->getOperand(2).isReg() &&
116+
MI->getOperand(1).getReg() == MI->getOperand(2).getReg()}]>;
117+
def M3ShiftExtPred : SchedPredicate<[{TII->isExynosShiftExtFast(*MI)}]>;
118118

119119
//===----------------------------------------------------------------------===//
120120
// Coarse scheduling model.
@@ -137,15 +137,15 @@ def M3WriteAD : SchedWriteRes<[M3UnitALU,
137137
let NumMicroOps = 2; }
138138
def M3WriteC1 : SchedWriteRes<[M3UnitC]> { let Latency = 1; }
139139
def M3WriteC2 : SchedWriteRes<[M3UnitC]> { let Latency = 2; }
140-
def M3WriteAX : SchedWriteVariant<[SchedVar<M3ResetFastPred, [M3WriteZ0]>,
141-
SchedVar<M3ShiftLeftFastPred, [M3WriteA1]>,
142-
SchedVar<NoSchedPred, [M3WriteAA]>]>;
143-
def M3WriteAY : SchedWriteVariant<[SchedVar<M3RotateRightFastPred, [M3WriteA1]>,
144-
SchedVar<NoSchedPred, [M3WriteAA]>]>;
140+
def M3WriteAX : SchedWriteVariant<[SchedVar<M3ResetPred, [M3WriteZ0]>,
141+
SchedVar<M3ShiftExtPred, [M3WriteA1]>,
142+
SchedVar<NoSchedPred, [M3WriteAA]>]>;
143+
def M3WriteAY : SchedWriteVariant<[SchedVar<M3RotatePred, [M3WriteA1]>,
144+
SchedVar<NoSchedPred, [M3WriteAA]>]>;
145145

146146
def M3WriteB1 : SchedWriteRes<[M3UnitB]> { let Latency = 1; }
147-
def M3WriteBX : SchedWriteVariant<[SchedVar<M3BranchLinkFastPred, [M3WriteAB]>,
148-
SchedVar<NoSchedPred, [M3WriteAC]>]>;
147+
def M3WriteBX : SchedWriteVariant<[SchedVar<M3BranchLinkPred, [M3WriteAB]>,
148+
SchedVar<NoSchedPred, [M3WriteAC]>]>;
149149

150150
def M3WriteL4 : SchedWriteRes<[M3UnitL]> { let Latency = 4; }
151151
def M3WriteL5 : SchedWriteRes<[M3UnitL]> { let Latency = 5; }
@@ -165,8 +165,8 @@ def M3WriteLD : SchedWriteRes<[M3UnitA,
165165
def M3WriteLH : SchedWriteRes<[]> { let Latency = 5;
166166
let NumMicroOps = 0; }
167167

168-
def M3WriteLX : SchedWriteVariant<[SchedVar<M3ShiftLeftFastPred, [M3WriteL5]>,
169-
SchedVar<NoSchedPred, [M3WriteLB]>]>;
168+
def M3WriteLX : SchedWriteVariant<[SchedVar<M3ShiftExtPred, [M3WriteL5]>,
169+
SchedVar<NoSchedPred, [M3WriteLB]>]>;
170170

171171
def M3WriteS1 : SchedWriteRes<[M3UnitS]> { let Latency = 1; }
172172
def M3WriteSA : SchedWriteRes<[M3UnitA,
@@ -180,10 +180,10 @@ def M3WriteSC : SchedWriteRes<[M3UnitA,
180180
M3UnitS]> { let Latency = 2;
181181
let NumMicroOps = 2; }
182182

183-
def M3WriteSX : SchedWriteVariant<[SchedVar<M3ShiftLeftFastPred, [M3WriteS1]>,
184-
SchedVar<NoSchedPred, [M3WriteSB]>]>;
185-
def M3WriteSY : SchedWriteVariant<[SchedVar<M3ShiftLeftFastPred, [M3WriteS1]>,
186-
SchedVar<NoSchedPred, [M3WriteSC]>]>;
183+
def M3WriteSX : SchedWriteVariant<[SchedVar<M3ShiftExtPred, [M3WriteS1]>,
184+
SchedVar<NoSchedPred, [M3WriteSB]>]>;
185+
def M3WriteSY : SchedWriteVariant<[SchedVar<M3ShiftExtPred, [M3WriteS1]>,
186+
SchedVar<NoSchedPred, [M3WriteSC]>]>;
187187

188188
def M3ReadAdrBase : SchedReadVariant<[SchedVar<ScaledIdxPred, [ReadDefault]>,
189189
SchedVar<NoSchedPred, [ReadDefault]>]>;
@@ -481,8 +481,8 @@ def M3WriteAES : SchedWriteRes<[M3UnitNCRY]> { let Latency = 1; }
481481
def M3ReadAES : SchedReadAdvance<1, [M3WriteAES]>;
482482
def M3ReadFMAC : SchedReadAdvance<1, [M3WriteFMAC4,
483483
M3WriteFMAC5]>;
484-
def M3WriteMOVI : SchedWriteVariant<[SchedVar<M3ResetFastPred, [M3WriteZ0]>,
485-
SchedVar<NoSchedPred, [M3WriteNALU1]>]>;
484+
def M3WriteMOVI : SchedWriteVariant<[SchedVar<M3ResetPred, [M3WriteZ0]>,
485+
SchedVar<NoSchedPred, [M3WriteNALU1]>]>;
486486
def M3ReadNMUL : SchedReadAdvance<1, [M3WriteNMUL3]>;
487487

488488
// Branch instructions

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