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[AArch64] Fix feature flags dependecies (#90612)
This patch removes FEAT_FPMR from list of available of architecture features, instead enabling FMPR register by default. Additionally dependencies between architectural features are added and fixed.
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7 files changed

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‎clang/test/Driver/aarch64-v95a.c

Lines changed: 2 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -6,22 +6,18 @@
66
// RUN: %clang -target aarch64 -mlittle-endian -march=armv9.5-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV95A %s
77
// RUN: %clang -target aarch64_be -mlittle-endian -march=armv9.5a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV95A %s
88
// RUN: %clang -target aarch64_be -mlittle-endian -march=armv9.5-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV95A %s
9-
// GENERICV95A: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.5a"
9+
// GENERICV95A: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.5a"{{.*}} "-target-feature" "+cpa"{{.*}} "-target-feature" "+faminmax"{{.*}} "-target-feature" "+lut"
1010

1111
// RUN: %clang -target aarch64_be -march=armv9.5a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV95A-BE %s
1212
// RUN: %clang -target aarch64_be -march=armv9.5-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV95A-BE %s
1313
// RUN: %clang -target aarch64 -mbig-endian -march=armv9.5a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV95A-BE %s
1414
// RUN: %clang -target aarch64 -mbig-endian -march=armv9.5-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV95A-BE %s
1515
// RUN: %clang -target aarch64_be -mbig-endian -march=armv9.5a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV95A-BE %s
1616
// RUN: %clang -target aarch64_be -mbig-endian -march=armv9.5-a -### -c %s 2>&1 | FileCheck -check-prefix=GENERICV95A-BE %s
17-
// GENERICV95A-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.5a"
17+
// GENERICV95A-BE: "-cc1"{{.*}} "-triple" "aarch64_be{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.5a"{{.*}} "-target-feature" "+cpa"{{.*}} "-target-feature" "+faminmax"{{.*}} "-target-feature" "+lut"
1818

1919
// ===== Features supported on aarch64 =====
2020

21-
// RUN: %clang -target aarch64 -march=armv9.5a+cpa -### -c %s 2>&1 | FileCheck -check-prefix=V95A-CPA %s
22-
// RUN: %clang -target aarch64 -march=armv9.5-a+cpa -### -c %s 2>&1 | FileCheck -check-prefix=V95A-CPA %s
23-
// V95A-CPA: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.5a"{{.*}} "-target-feature" "+cpa"
24-
2521
// RUN: %clang -target aarch64 -march=armv9.5a+pauth-lr -### -c %s 2>&1 | FileCheck -check-prefix=V95A-PAUTHLR %s
2622
// RUN: %clang -target aarch64 -march=armv9.5-a+pauth-lr -### -c %s 2>&1 | FileCheck -check-prefix=V95A-PAUTHLR %s
2723
// V95A-PAUTHLR: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.5a"{{.*}} "-target-feature" "+pauth-lr"

‎llvm/lib/Target/AArch64/AArch64Features.td

Lines changed: 21 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -223,13 +223,6 @@ def FeatureSVE : Extension<"sve", "SVE",
223223
"Enable Scalable Vector Extension (SVE) instructions (FEAT_SVE)", [FeatureFullFP16],
224224
"FEAT_SVE", "+sve,+fullfp16,+fp-armv8,+neon", 310>;
225225

226-
def FeatureFPMR : Extension<"fpmr", "FPMR",
227-
"Enable FPMR Register (FEAT_FPMR)">;
228-
229-
let FMVDependencies = "+fpmr" in
230-
def FeatureFP8 : Extension<"fp8", "FP8",
231-
"Enable FP8 instructions (FEAT_FP8)">;
232-
233226
// This flag is currently still labeled as Experimental, but when fully
234227
// implemented this should tell the compiler to use the zeroing pseudos to
235228
// benefit from the reverse instructions (e.g. SUB vs SUBR) if the inactive
@@ -667,41 +660,44 @@ def FeatureSME2p1 : Extension<"sme2p1", "SME2p1",
667660
def FeatureFAMINMAX: Extension<"faminmax", "FAMINMAX",
668661
"Enable FAMIN and FAMAX instructions (FEAT_FAMINMAX)">;
669662

670-
let FMVDependencies = "+fpmr" in
663+
def FeatureLUT: Extension<"lut", "LUT",
664+
"Enable Lookup Table instructions (FEAT_LUT)">;
665+
666+
def FeatureFP8 : Extension<"fp8", "FP8",
667+
"Enable FP8 instructions (FEAT_FP8)", [FeatureFAMINMAX, FeatureLUT, FeatureBF16]>;
668+
671669
def FeatureFP8FMA : Extension<"fp8fma", "FP8FMA",
672-
"Enable fp8 multiply-add instructions (FEAT_FP8FMA)">;
670+
"Enable fp8 multiply-add instructions (FEAT_FP8FMA)", [FeatureFP8]>;
673671

674672
let FMVDependencies = "+sme2" in
675673
def FeatureSSVE_FP8FMA : Extension<"ssve-fp8fma", "SSVE_FP8FMA",
676-
"Enable SVE2 fp8 multiply-add instructions (FEAT_SSVE_FP8FMA)", [FeatureSME2]>;
674+
"Enable SVE2 fp8 multiply-add instructions (FEAT_SSVE_FP8FMA)", [FeatureSME2, FeatureFP8]>;
677675

676+
def FeatureFP8DOT4: Extension<"fp8dot4", "FP8DOT4",
677+
"Enable fp8 4-way dot instructions (FEAT_FP8DOT4)", [FeatureFP8FMA]>;
678+
678679
def FeatureFP8DOT2: Extension<"fp8dot2", "FP8DOT2",
679-
"Enable fp8 2-way dot instructions (FEAT_FP8DOT2)">;
680+
"Enable fp8 2-way dot instructions (FEAT_FP8DOT2)", [FeatureFP8DOT4]>;
680681

681682
let FMVDependencies = "+sme2" in
682-
def FeatureSSVE_FP8DOT2 : Extension<"ssve-fp8dot2", "SSVE_FP8DOT2",
683-
"Enable SVE2 fp8 2-way dot product instructions (FEAT_SSVE_FP8DOT2)", [FeatureSME2]>;
684-
685-
def FeatureFP8DOT4: Extension<"fp8dot4", "FP8DOT4",
686-
"Enable fp8 4-way dot instructions (FEAT_FP8DOT4)">;
683+
def FeatureSSVE_FP8DOT4 : Extension<"ssve-fp8dot4", "SSVE_FP8DOT4",
684+
"Enable SVE2 fp8 4-way dot product instructions (FEAT_SSVE_FP8DOT4)", [FeatureSSVE_FP8FMA]>;
687685

688686
let FMVDependencies = "+sme2" in
689-
def FeatureSSVE_FP8DOT4 : Extension<"ssve-fp8dot4", "SSVE_FP8DOT4",
690-
"Enable SVE2 fp8 4-way dot product instructions (FEAT_SSVE_FP8DOT4)", [FeatureSME2]>;
691-
def FeatureLUT: Extension<"lut", "LUT",
692-
"Enable Lookup Table instructions (FEAT_LUT)">;
687+
def FeatureSSVE_FP8DOT2 : Extension<"ssve-fp8dot2", "SSVE_FP8DOT2",
688+
"Enable SVE2 fp8 2-way dot product instructions (FEAT_SSVE_FP8DOT2)", [FeatureSSVE_FP8DOT4]>;
693689

694690
def FeatureSME_LUTv2 : Extension<"sme-lutv2", "SME_LUTv2",
695691
"Enable Scalable Matrix Extension (SME) LUTv2 instructions (FEAT_SME_LUTv2)">;
696692

697-
let FMVDependencies = "+fp8,+sme2" in
698-
def FeatureSMEF8F16 : Extension<"sme-f8f16", "SMEF8F16",
699-
"Enable Scalable Matrix Extension (SME) F8F16 instructions(FEAT_SME_F8F16)", [FeatureSME2, FeatureFP8]>;
700-
701693
let FMVDependencies = "+sme2,+fp8" in
702694
def FeatureSMEF8F32 : Extension<"sme-f8f32", "SMEF8F32",
703695
"Enable Scalable Matrix Extension (SME) F8F32 instructions (FEAT_SME_F8F32)", [FeatureSME2, FeatureFP8]>;
704696

697+
let FMVDependencies = "+fp8,+sme2" in
698+
def FeatureSMEF8F16 : Extension<"sme-f8f16", "SMEF8F16",
699+
"Enable Scalable Matrix Extension (SME) F8F16 instructions(FEAT_SME_F8F16)", [FeatureSMEF8F32]>;
700+
705701
def FeatureAppleA7SysReg : SubtargetFeature<"apple-a7-sysreg", "HasAppleA7SysReg", "true",
706702
"Apple A7 (the CPU formerly known as Cyclone)">;
707703

@@ -869,7 +865,7 @@ def HasV9_4aOps : Architecture64<9, 4, "a", "v9.4a",
869865
FeatureRASv2])>;
870866
def HasV9_5aOps : Architecture64<9, 5, "a", "v9.5a",
871867
[HasV9_4aOps, FeatureCPA],
872-
!listconcat(HasV9_4aOps.DefaultExts, [FeatureCPA])>;
868+
!listconcat(HasV9_4aOps.DefaultExts, [FeatureCPA, FeatureLUT, FeatureFAMINMAX])>;
873869
def HasV8_0rOps : Architecture64<8, 0, "r", "v8r",
874870
[ //v8.1
875871
FeatureCRC, FeaturePAN, FeatureLSE, FeatureCONTEXTIDREL2,

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -171,8 +171,6 @@ def HasSME2 : Predicate<"Subtarget->hasSME2()">,
171171
AssemblerPredicateWithAll<(all_of FeatureSME2), "sme2">;
172172
def HasSME2p1 : Predicate<"Subtarget->hasSME2p1()">,
173173
AssemblerPredicateWithAll<(all_of FeatureSME2p1), "sme2p1">;
174-
def HasFPMR : Predicate<"Subtarget->hasFPMR()">,
175-
AssemblerPredicateWithAll<(all_of FeatureFPMR), "fpmr">;
176174
def HasFP8 : Predicate<"Subtarget->hasFP8()">,
177175
AssemblerPredicateWithAll<(all_of FeatureFP8), "fp8">;
178176
def HasFAMINMAX : Predicate<"Subtarget->hasFAMINMAX()">,

‎llvm/lib/Target/AArch64/AArch64SystemOperands.td

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1943,11 +1943,9 @@ def : RWSysReg<"PM", 0b11, 0b000, 0b0100, 0b0011, 0b001>;
19431943
// 2023 ISA Extension
19441944
// AArch64 Floating-point Mode Register controls behaviors of the FP8
19451945
// instructions (FEAT_FPMR)
1946-
let Requires = [{ {AArch64::FeatureFPMR} }] in {
19471946
// Op0 Op1 CRn CRm Op2
19481947
def : ROSysReg<"ID_AA64FPFR0_EL1", 0b11, 0b000, 0b0000, 0b0100, 0b111>;
19491948
def : RWSysReg<"FPMR", 0b11, 0b011, 0b0100, 0b0100, 0b010>;
1950-
}
19511949

19521950
// v9.5a Software Stepping Enhancements (FEAT_STEP2)
19531951
// Op0 Op1 CRn CRm Op2

‎llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3718,7 +3718,6 @@ static const struct Extension {
37183718
{"sb", {AArch64::FeatureSB}},
37193719
{"ssbs", {AArch64::FeatureSSBS}},
37203720
{"tme", {AArch64::FeatureTME}},
3721-
{"fpmr", {AArch64::FeatureFPMR}},
37223721
{"fp8", {AArch64::FeatureFP8}},
37233722
{"faminmax", {AArch64::FeatureFAMINMAX}},
37243723
{"fp8fma", {AArch64::FeatureFP8FMA}},
@@ -3731,7 +3730,7 @@ static const struct Extension {
37313730
{"sme-lutv2", {AArch64::FeatureSME_LUTv2}},
37323731
{"sme-f8f16", {AArch64::FeatureSMEF8F16}},
37333732
{"sme-f8f32", {AArch64::FeatureSMEF8F32}},
3734-
{"sme-fa64", {AArch64::FeatureSMEFA64}},
3733+
{"sme-fa64", {AArch64::FeatureSMEFA64}},
37353734
{"cpa", {AArch64::FeatureCPA}},
37363735
{"tlbiw", {AArch64::FeatureTLBIW}},
37373736
};

‎llvm/test/MC/AArch64/FP8/system-regs.s

Lines changed: 9 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1,32 +1,28 @@
1-
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+fpmr < %s \
1+
// RUN: llvm-mc -triple=aarch64 -show-encoding < %s \
22
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3-
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
4-
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
5-
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+fpmr < %s \
6-
// RUN: | llvm-objdump -d --mattr=+fpmr - | FileCheck %s --check-prefix=CHECK-INST
7-
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+fpmr < %s \
8-
// RUN: | llvm-objdump --mattr=-fpmr -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
3+
// RUN: llvm-mc -triple=aarch64 -filetype=obj < %s \
4+
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-INST
5+
// RUN: llvm-mc -triple=aarch64 -filetype=obj < %s \
6+
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
97

108
// --------------------------------------------------------------------------//
119
// read
1210

1311
mrs x3, FPMR
1412
// CHECK-INST: mrs x3, FPMR
1513
// CHECK-ENCODING: [0x43,0x44,0x3b,0xd5]
16-
// CHECK-ERROR: expected readable system register
17-
// CHECK-UNKNOWN: d53b4443 mrs x3, S3_3_C4_C4_2
14+
// CHECK-UNKNOWN: d53b4443 mrs x3, FPMR
15+
1816

1917
mrs x3, ID_AA64FPFR0_EL1
2018
// CHECK-INST: mrs x3, ID_AA64FPFR0_EL1
2119
// CHECK-ENCODING: [0xe3,0x04,0x38,0xd5]
22-
// CHECK-ERROR: expected readable system register
23-
// CHECK-UNKNOWN: d53804e3 mrs x3, S3_0_C0_C4_7
20+
// CHECK-UNKNOWN: d53804e3 mrs x3, ID_AA64FPFR0_EL1
2421

2522
// --------------------------------------------------------------------------//
2623
// write
2724

2825
msr FPMR, x3
2926
// CHECK-INST: msr FPMR, x3
3027
// CHECK-ENCODING: [0x43,0x44,0x1b,0xd5]
31-
// CHECK-ERROR: expected writable system register or pstate
32-
// CHECK-UNKNOWN: d51b4443 msr S3_3_C4_C4_2, x3
28+
// CHECK-UNKNOWN: d51b4443 msr FPMR, x3

‎llvm/unittests/TargetParser/TargetParserTest.cpp

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1996,7 +1996,6 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
19961996
AArch64::AEK_D128, AArch64::AEK_LSE128,
19971997
AArch64::AEK_SPECRES2, AArch64::AEK_RASV2,
19981998
AArch64::AEK_ITE, AArch64::AEK_GCS,
1999-
AArch64::AEK_FPMR, AArch64::AEK_FP8,
20001999
AArch64::AEK_FAMINMAX, AArch64::AEK_FP8FMA,
20012000
AArch64::AEK_SSVE_FP8FMA, AArch64::AEK_FP8DOT2,
20022001
AArch64::AEK_SSVE_FP8DOT2, AArch64::AEK_FP8DOT4,
@@ -2005,7 +2004,8 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
20052004
AArch64::AEK_SMEF8F32, AArch64::AEK_SMEFA64,
20062005
AArch64::AEK_CPA, AArch64::AEK_PAUTHLR,
20072006
AArch64::AEK_TLBIW, AArch64::AEK_JSCVT,
2008-
AArch64::AEK_FCMA,
2007+
AArch64::AEK_FCMA, AArch64::AEK_FP8,
2008+
20092009
};
20102010

20112011
std::vector<StringRef> Features;
@@ -2078,7 +2078,6 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
20782078
EXPECT_TRUE(llvm::is_contained(Features, "+specres2"));
20792079
EXPECT_TRUE(llvm::is_contained(Features, "+ite"));
20802080
EXPECT_TRUE(llvm::is_contained(Features, "+gcs"));
2081-
EXPECT_TRUE(llvm::is_contained(Features, "+fpmr"));
20822081
EXPECT_TRUE(llvm::is_contained(Features, "+fp8"));
20832082
EXPECT_TRUE(llvm::is_contained(Features, "+faminmax"));
20842083
EXPECT_TRUE(llvm::is_contained(Features, "+fp8fma"));
@@ -2224,7 +2223,6 @@ TEST(TargetParserTest, AArch64ArchExtFeature) {
22242223
{"predres2", "nopredres2", "+specres2", "-specres2"},
22252224
{"rasv2", "norasv2", "+rasv2", "-rasv2"},
22262225
{"gcs", "nogcs", "+gcs", "-gcs"},
2227-
{"fpmr", "nofpmr", "+fpmr", "-fpmr"},
22282226
{"fp8", "nofp8", "+fp8", "-fp8"},
22292227
{"faminmax", "nofaminmax", "+faminmax", "-faminmax"},
22302228
{"fp8fma", "nofp8fma", "+fp8fma", "-fp8fma"},

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