fix more langref mistakes with aarch64 calling convention

vtjnash · vtjnash · commit 78745ede2a51 · 2025-02-12T10:43:25.000-05:00
The calling convention previously stated that X9 and X15 were
callee-preserved, but the implementation of AArch64FrameLowering.cpp
uses those as scratch registers and does not actually preserve it.
diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst
@@ -410,8 +410,8 @@ added in the future:
       calling convention: on most platforms, they are not preserved and need to
       be saved by the caller, but on Windows, xmm6-xmm15 are preserved.
 
-    - On AArch64 the callee preserve all general purpose registers, except X0-X8
-      and X16-X18.
+    - On AArch64 the callee preserve all general purpose registers, except X0-X9
+      and X15-X18. X9 can be used as a scratch register.
 
     The idea behind this convention is to support calls to runtime functions
     that have a hot path and a cold path. The hot path is usually a small piece
@@ -447,9 +447,9 @@ added in the future:
       R11. R11 can be used as a scratch register. Furthermore it also preserves
       all floating-point registers (XMMs/YMMs).
 
-    - On AArch64 the callee preserve all general purpose registers, except X0-X8
-      and X16-X18. Furthermore it also preserves lower 128 bits of V8-V31 SIMD -
-      floating point registers.
+    - On AArch64 the callee preserve all general purpose registers, except X0-X9
+      and X15-X18. Furthermore it also preserves lower 128 bits of V8-V31 SIMD -
+      floating point registers. X9 can be used as a scratch register.
 
     The idea behind this convention is to support calls to runtime functions
     that don't need to call out to any other functions.
diff --git a/llvm/lib/Target/AArch64/AArch64CallingConvention.td b/llvm/lib/Target/AArch64/AArch64CallingConvention.td
@@ -691,7 +691,7 @@ def CSR_AArch64_NoRegs : CalleeSavedRegs<(add)>;
 def CSR_AArch64_NoneRegs : CalleeSavedRegs<(add LR, FP)>;
 
 def CSR_AArch64_RT_MostRegs :  CalleeSavedRegs<(add CSR_AArch64_AAPCS,
-                                                (sequence "X%u", 9, 15))>;
+                                                (sequence "X%u", 10, 14))>;
 
 def CSR_AArch64_RT_AllRegs :  CalleeSavedRegs<(add CSR_AArch64_RT_MostRegs,
                                                 (sequence "Q%u", 8, 31))>;
diff --git a/llvm/test/CodeGen/AArch64/arm64-preserve-all.ll b/llvm/test/CodeGen/AArch64/arm64-preserve-all.ll
@@ -7,8 +7,8 @@ target triple = "aarch64-unknown-linux-gnu"
 declare void @normal_cc()
 
 ; Caller: preserve_allcc; callee: normalcc. Normally callee saved registers
-; x9~x15 need to be spilled. Since most of them will be spilled in pairs in
-; reverse order, we only check the odd number ones due to FileCheck not
+; x10~x14 need to be spilled. Since most of them will be spilled in pairs in
+; reverse order, we only check the even number ones due to FileCheck not
 ; matching the same line of assembly twice.
 ; CHECK-LABEL: preserve_all
 ; CHECK-DAG: {{st[rp]}} {{(q[0-9]+, )?q8(, x[0-9]+)?}}, [sp, #{{[-0-9]+}}]
@@ -22,21 +22,23 @@ declare void @normal_cc()
 ; CHECK-DAG: {{st[rp]}} {{(q[0-9]+, )?q26(, x[0-9]+)?}}, [sp, #{{[-0-9]+}}]
 ; CHECK-DAG: {{st[rp]}} {{(q[0-9]+, )?q28(, x[0-9]+)?}}, [sp, #{{[-0-9]+}}]
 ; CHECK-DAG: {{st[rp]}} {{(q[0-9]+, )?q30(, x[0-9]+)?}}, [sp, #{{[-0-9]+}}]
-; CHECK-DAG: {{st[rp]}} {{(x[0-9]+, )?x9(, x[0-9]+)?}}, [sp, #{{[-0-9]+}}]
-; CHECK-DAG: {{st[rp]}} {{(x[0-9]+, )?x11(, x[0-9]+)?}}, [sp, #{{[-0-9]+}}]
-; CHECK-DAG: {{st[rp]}} {{(x[0-9]+, )?x13(, x[0-9]+)?}}, [sp, #{{[-0-9]+}}]
-; CHECK-DAG: {{st[rp]}} {{(x[0-9]+, )?x15(, x[0-9]+)?}}, [sp, #{{[-0-9]+}}]
+; CHECK-DAG: {{st[rp]}} {{(x[0-9]+, )?x10(, x[0-9]+)?}}, [sp, #{{[-0-9]+}}]
+; CHECK-DAG: {{st[rp]}} {{(x[0-9]+, )?x12(, x[0-9]+)?}}, [sp, #{{[-0-9]+}}]
+; CHECK-DAG: {{st[rp]}} {{(x[0-9]+, )?x14(, x[0-9]+)?}}, [sp, #{{[-0-9]+}}]
 define preserve_allcc void @preserve_all() {
   call void @normal_cc()
   ret void
 }
 
 ; Caller: normalcc; callee: preserve_allcc. x9/q9 does not need to be spilled.
-; The same holds for other x and q registers, but we only check x9 and q9.
+; The same holds for other x and q registers, but we only check x9, x11, and q9.
 ; CHECK-LABEL: normal_cc_caller
 ; CHECK-NOT: stp {{x[0-9]+}}, x9, [sp, #{{[-0-9]+}}]
 ; CHECK-NOT: stp x9, {{x[0-9]+}}, [sp, #{{[-0-9]+}}]
 ; CHECK-NOT: str x9, [sp, {{#[-0-9]+}}]
+; CHECK-NOT: stp {{x[0-9]+}}, x11, [sp, #{{[-0-9]+}}]
+; CHECK-NOT: stp x10, {{x[0-9]+}}, [sp, #{{[-0-9]+}}]
+; CHECK-NOT: str x10, [sp, {{#[-0-9]+}}]
 ; CHECK-NOT: stp {{q[0-9]+}}, q9, [sp, #{{[-0-9]+}}]
 ; CHECK-NOT: stp q9, {{q[0-9]+}}, [sp, #{{[-0-9]+}}]
 ; CHECK-NOT: str q9, [sp, {{#[-0-9]+}}]
diff --git a/llvm/test/CodeGen/AArch64/arm64-preserve-most.ll b/llvm/test/CodeGen/AArch64/arm64-preserve-most.ll
@@ -7,25 +7,24 @@ target triple = "aarch64-unknown-linux-gnu"
 declare void @normal_cc()
 
 ; Caller: preserve_mostcc; callee: normalcc. Normally callee saved registers
-; x9~x15 need to be spilled. Since most of them will be spilled in pairs in
-; reverse order, we only check the odd number ones due to FileCheck not
+; x10~x14 need to be spilled. Since most of them will be spilled in pairs in
+; reverse order, we only check the even number ones due to FileCheck not
 ; matching the same line of assembly twice.
 ; CHECK-LABEL: preserve_most
-; CHECK-DAG: {{st[rp]}} {{(x[0-9]+, )?x9(, x[0-9]+)?}}, [sp, #{{[-0-9]+}}]
-; CHECK-DAG: {{st[rp]}} {{(x[0-9]+, )?x11(, x[0-9]+)?}}, [sp, #{{[-0-9]+}}]
-; CHECK-DAG: {{st[rp]}} {{(x[0-9]+, )?x13(, x[0-9]+)?}}, [sp, #{{[-0-9]+}}]
-; CHECK-DAG: {{st[rp]}} {{(x[0-9]+, )?x15(, x[0-9]+)?}}, [sp, #{{[-0-9]+}}]
+; CHECK-DAG: {{st[rp]}} {{(x[0-9]+, )?x10(, x[0-9]+)?}}, [sp, #{{[-0-9]+}}]
+; CHECK-DAG: {{st[rp]}} {{(x[0-9]+, )?x12(, x[0-9]+)?}}, [sp, #{{[-0-9]+}}]
+; CHECK-DAG: {{st[rp]}} {{(x[0-9]+, )?x14(, x[0-9]+)?}}, [sp, #{{[-0-9]+}}]
 define preserve_mostcc void @preserve_most() {
   call void @normal_cc()
   ret void
 }
 
-; Caller: normalcc; callee: preserve_mostcc. x9 does not need to be spilled.
-; The same holds for x10 through x15, but we only check x9.
+; Caller: normalcc; callee: preserve_mostcc. x9 does need to be spilled, but not x10 to x14.
+; (we only check x10).
 ; CHECK-LABEL: normal_cc_caller
-; CHECK-NOT: stp {{x[0-9]+}}, x9, [sp, #{{[-0-9]+}}]
-; CHECK-NOT: stp x9, {{x[0-9]+}}, [sp, #{{[-0-9]+}}]
-; CHECK-NOT: str x9, [sp, {{#[-0-9]+}}]
+; CHECK-NOT: stp {{x[0-9]+}}, x10, [sp, #{{[-0-9]+}}]
+; CHECK-NOT: stp x10, {{x[0-9]+}}, [sp, #{{[-0-9]+}}]
+; CHECK-NOT: str x10, [sp, {{#[-0-9]+}}]
 define dso_local void @normal_cc_caller() {
 entry:
   %v = alloca i32, align 4
diff --git a/llvm/test/CodeGen/AArch64/preserve.ll b/llvm/test/CodeGen/AArch64/preserve.ll
diff --git a/llvm/test/CodeGen/AArch64/trampoline.ll b/llvm/test/CodeGen/AArch64/trampoline.ll
