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[AMDGPU][MC][NFC] Refine SMEM store, probe and discard definitions.
Reviewed By: dp Differential Revision: https://reviews.llvm.org/D131968
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‎llvm/lib/Target/AMDGPU/SMInstructions.td

Lines changed: 37 additions & 62 deletions
Original file line numberDiff line numberDiff line change
@@ -102,21 +102,19 @@ def SGPR_IMM_Offset : OffsetMode<1, 1, "_SGPR_IMM",
102102
(ins SReg_32:$soffset, smem_offset_mod:$offset),
103103
"$soffset$offset">;
104104

105-
class SM_Probe_Pseudo <string opName, string variant, RegisterClass baseClass,
106-
dag offsets, string asmOffsets,
107-
bit hasOffset, bit hasSOffset>
105+
class SM_Probe_Pseudo <string opName, RegisterClass baseClass, OffsetMode offsets>
108106
: SM_Pseudo<opName, (outs),
109-
!con((ins i8imm:$sdata, baseClass:$sbase), offsets),
110-
" $sdata, $sbase, " # asmOffsets> {
107+
!con((ins i8imm:$sdata, baseClass:$sbase), offsets.Ins),
108+
" $sdata, $sbase, " # offsets.Asm> {
111109
let mayLoad = 0;
112110
let mayStore = 0;
113111
let has_glc = 0;
114112
let LGKM_CNT = 0;
115113
let ScalarStore = 0;
116114
let hasSideEffects = 1;
117-
let has_offset = hasOffset;
118-
let has_soffset = hasSOffset;
119-
let PseudoInstr = opName # variant;
115+
let has_offset = offsets.HasOffset;
116+
let has_soffset = offsets.HasSOffset;
117+
let PseudoInstr = opName # offsets.Variant;
120118
}
121119

122120
class SM_Load_Pseudo <string opName, RegisterClass baseClass,
@@ -135,30 +133,34 @@ class SM_Load_Pseudo <string opName, RegisterClass baseClass,
135133
}
136134

137135
class SM_Store_Pseudo <string opName, RegisterClass baseClass,
138-
RegisterClass srcClass, dag ins, string asmOps>
139-
: SM_Pseudo<opName, (outs), ins, asmOps, []> {
136+
RegisterClass srcClass, OffsetMode offsets>
137+
: SM_Pseudo<opName, (outs), !con((ins srcClass:$sdata, baseClass:$sbase),
138+
offsets.Ins, (ins CPol:$cpol)),
139+
" $sdata, $sbase, " # offsets.Asm # "$cpol"> {
140140
RegisterClass BaseClass = baseClass;
141141
RegisterClass SrcClass = srcClass;
142142
let mayLoad = 0;
143143
let mayStore = 1;
144144
let has_glc = 1;
145145
let has_dlc = 1;
146+
let has_offset = offsets.HasOffset;
147+
let has_soffset = offsets.HasSOffset;
146148
let ScalarStore = 1;
149+
let PseudoInstr = opName # offsets.Variant;
147150
}
148151

149-
class SM_Discard_Pseudo <string opName, string variant, dag offsets,
150-
string asmOffsets, bit hasOffset, bit hasSOffset>
151-
: SM_Pseudo<opName, (outs), !con((ins SReg_64:$sbase), offsets),
152-
" $sbase, " # asmOffsets> {
152+
class SM_Discard_Pseudo <string opName, OffsetMode offsets>
153+
: SM_Pseudo<opName, (outs), !con((ins SReg_64:$sbase), offsets.Ins),
154+
" $sbase, " # offsets.Asm> {
153155
let mayLoad = 0;
154156
let mayStore = 0;
155157
let has_glc = 0;
156158
let has_sdst = 0;
157159
let ScalarStore = 0;
158160
let hasSideEffects = 1;
159-
let has_offset = hasOffset;
160-
let has_soffset = hasSOffset;
161-
let PseudoInstr = opName # variant;
161+
let has_offset = offsets.HasOffset;
162+
let has_soffset = offsets.HasSOffset;
163+
let PseudoInstr = opName # offsets.Variant;
162164
}
163165

164166
multiclass SM_Pseudo_Loads<string opName,
@@ -172,37 +174,15 @@ multiclass SM_Pseudo_Loads<string opName,
172174
multiclass SM_Pseudo_Stores<string opName,
173175
RegisterClass baseClass,
174176
RegisterClass srcClass> {
175-
def _IMM : SM_Store_Pseudo <opName, baseClass, srcClass,
176-
(ins srcClass:$sdata, baseClass:$sbase, i32imm:$offset, CPol:$cpol),
177-
" $sdata, $sbase, $offset$cpol"> {
178-
let has_offset = 1;
179-
let PseudoInstr = opName # "_IMM";
180-
}
181-
182-
def _SGPR : SM_Store_Pseudo <opName, baseClass, srcClass,
183-
(ins srcClass:$sdata, baseClass:$sbase, SReg_32:$soffset, CPol:$cpol),
184-
" $sdata, $sbase, $soffset$cpol"> {
185-
let has_soffset = 1;
186-
let PseudoInstr = opName # "_SGPR";
187-
}
188-
189-
def _SGPR_IMM : SM_Store_Pseudo <opName, baseClass, srcClass,
190-
(ins srcClass:$sdata, baseClass:$sbase, SReg_32:$soffset, i32imm:$offset,
191-
CPol:$cpol),
192-
" $sdata, $sbase, $soffset$offset$cpol"> {
193-
let has_offset = 1;
194-
let has_soffset = 1;
195-
let PseudoInstr = opName # "_SGPR_IMM";
196-
}
177+
def _IMM : SM_Store_Pseudo <opName, baseClass, srcClass, IMM_Offset>;
178+
def _SGPR : SM_Store_Pseudo <opName, baseClass, srcClass, SGPR_Offset>;
179+
def _SGPR_IMM : SM_Store_Pseudo <opName, baseClass, srcClass, SGPR_IMM_Offset>;
197180
}
198181

199182
multiclass SM_Pseudo_Discards<string opName> {
200-
def _IMM : SM_Discard_Pseudo <opName, "_IMM",
201-
(ins smem_offset:$offset), "$offset", 1, 0>;
202-
def _SGPR : SM_Discard_Pseudo <opName, "_SGPR",
203-
(ins SReg_32:$soffset), "$soffset", 0, 1>;
204-
def _SGPR_IMM : SM_Discard_Pseudo <opName, "_SGPR_IMM",
205-
(ins SReg_32:$soffset, smem_offset_mod:$offset), "$soffset$offset", 1, 1>;
183+
def _IMM : SM_Discard_Pseudo <opName, IMM_Offset>;
184+
def _SGPR : SM_Discard_Pseudo <opName, SGPR_Offset>;
185+
def _SGPR_IMM : SM_Discard_Pseudo <opName, SGPR_IMM_Offset>;
206186
}
207187

208188
class SM_Time_Pseudo<string opName, SDPatternOperator node = null_frag> : SM_Pseudo<
@@ -225,12 +205,9 @@ class SM_Inval_Pseudo <string opName, SDPatternOperator node = null_frag> : SM_P
225205
}
226206

227207
multiclass SM_Pseudo_Probe<string opName, RegisterClass baseClass> {
228-
def _IMM : SM_Probe_Pseudo <opName, "_IMM", baseClass,
229-
(ins smem_offset:$offset), "$offset", 1, 0>;
230-
def _SGPR : SM_Probe_Pseudo <opName, "_SGPR", baseClass,
231-
(ins SReg_32:$soffset), "$soffset", 0, 1>;
232-
def _SGPR_IMM : SM_Probe_Pseudo <opName, "_SGPR_IMM", baseClass,
233-
(ins SReg_32:$soffset, smem_offset_mod:$offset), "$soffset$offset", 1, 1>;
208+
def _IMM : SM_Probe_Pseudo <opName, baseClass, IMM_Offset>;
209+
def _SGPR : SM_Probe_Pseudo <opName, baseClass, SGPR_Offset>;
210+
def _SGPR_IMM : SM_Probe_Pseudo <opName, baseClass, SGPR_IMM_Offset>;
234211
}
235212

236213
class SM_WaveId_Pseudo<string opName, SDPatternOperator node> : SM_Pseudo<
@@ -605,23 +582,21 @@ class SMEM_Real_Store_Base_vi <bits<8> op, SM_Pseudo ps> : SMEM_Real_vi <op, ps>
605582
let Inst{12-6} = !if(ps.has_sdst, sdata{6-0}, ?);
606583
}
607584

608-
class SMEM_Real_Store_vi <bits<8> op, string ps, dag offsets>
609-
: SMEM_Real_Store_Base_vi <op, !cast<SM_Pseudo>(ps)> {
610-
RegisterClass SrcClass = !cast<SM_Store_Pseudo>(ps).SrcClass;
611-
RegisterClass BaseClass = !cast<SM_Store_Pseudo>(ps).BaseClass;
585+
class SMEM_Real_Store_vi <bits<8> op, string ps, OffsetMode offsets>
586+
: SMEM_Real_Store_Base_vi <op, !cast<SM_Pseudo>(ps # offsets.Variant)> {
587+
RegisterClass SrcClass = !cast<SM_Store_Pseudo>(ps # offsets.Variant).SrcClass;
588+
RegisterClass BaseClass = !cast<SM_Store_Pseudo>(ps # offsets.Variant).BaseClass;
612589
let InOperandList = !con((ins SrcClass:$sdata, BaseClass:$sbase),
613-
offsets, (ins CPol:$cpol));
590+
offsets.Ins, (ins CPol:$cpol));
614591
}
615592

616593
multiclass SM_Real_Stores_vi<bits<8> op, string ps> {
617-
def _IMM_vi : SMEM_Real_Store_vi <op, ps#_IMM, (ins smem_offset:$offset)>;
618-
def _SGPR_vi : SMEM_Real_Store_vi <op, ps#_SGPR, (ins SReg_32:$soffset)>;
619-
def _SGPR_alt_gfx9 : SMEM_Real_Store_vi <op, ps#"_SGPR",
620-
(ins SReg_32:$soffset)>,
594+
def _IMM_vi : SMEM_Real_Store_vi <op, ps, IMM_Offset>;
595+
def _SGPR_vi : SMEM_Real_Store_vi <op, ps, SGPR_Offset>;
596+
def _SGPR_alt_gfx9 : SMEM_Real_Store_vi <op, ps, SGPR_Offset>,
621597
SMEM_Real_SGPR_alt_gfx9;
622598
let IsGFX9SpecificEncoding = true in
623-
def _SGPR_IMM_gfx9 : SMEM_Real_Store_vi <
624-
op, ps#"_SGPR_IMM", (ins SReg_32:$soffset, smem_offset_mod:$offset)>;
599+
def _SGPR_IMM_gfx9 : SMEM_Real_Store_vi <op, ps, SGPR_IMM_Offset>;
625600
}
626601

627602
multiclass SM_Real_Probe_vi<bits<8> op, string ps> {

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