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Use llvm::has_single_bit<uint32_t> (NFC)
This patch replaces isPowerOf2_32 with llvm::has_single_bit<uint32_t> where the argument is wider than uint32_t.
1 parent 68e81d7 commit 7e6e636

20 files changed

+50
-39
lines changed

‎clang/lib/CodeGen/CGNonTrivialStruct.cpp

+2-1
Original file line numberDiff line numberDiff line change
@@ -522,7 +522,8 @@ struct GenBinaryFunc : CopyStructVisitor<Derived, IsMove>,
522522
Address SrcAddr = this->getAddrWithOffset(Addrs[SrcIdx], this->Start);
523523

524524
// Emit memcpy.
525-
if (Size.getQuantity() >= 16 || !llvm::isPowerOf2_32(Size.getQuantity())) {
525+
if (Size.getQuantity() >= 16 ||
526+
!llvm::has_single_bit<uint32_t>(Size.getQuantity())) {
526527
llvm::Value *SizeVal =
527528
llvm::ConstantInt::get(this->CGF->SizeTy, Size.getQuantity());
528529
DstAddr =

‎llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -535,7 +535,7 @@ bool CombinerHelper::matchCombineExtendingLoads(MachineInstr &MI,
535535

536536
// For non power-of-2 types, they will very likely be legalized into multiple
537537
// loads. Don't bother trying to match them into extending loads.
538-
if (!isPowerOf2_32(LoadValueTy.getSizeInBits()))
538+
if (!llvm::has_single_bit<uint32_t>(LoadValueTy.getSizeInBits()))
539539
return false;
540540

541541
// Find the preferred type aside from the any-extends (unless it's the only

‎llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -1018,7 +1018,7 @@ void IRTranslator::emitBitTestHeader(SwitchCG::BitTestBlock &B,
10181018

10191019
LLT MaskTy = SwitchOpTy;
10201020
if (MaskTy.getSizeInBits() > PtrTy.getSizeInBits() ||
1021-
!isPowerOf2_32(MaskTy.getSizeInBits()))
1021+
!llvm::has_single_bit<uint32_t>(MaskTy.getSizeInBits()))
10221022
MaskTy = LLT::scalar(PtrTy.getSizeInBits());
10231023
else {
10241024
// Ensure that the type will fit the mask value.

‎llvm/lib/CodeGen/GlobalISel/LegalityPredicates.cpp

+6-3
Original file line numberDiff line numberDiff line change
@@ -164,7 +164,8 @@ LegalityPredicate LegalityPredicates::sizeNotMultipleOf(unsigned TypeIdx,
164164
LegalityPredicate LegalityPredicates::sizeNotPow2(unsigned TypeIdx) {
165165
return [=](const LegalityQuery &Query) {
166166
const LLT QueryTy = Query.Types[TypeIdx];
167-
return QueryTy.isScalar() && !isPowerOf2_32(QueryTy.getSizeInBits());
167+
return QueryTy.isScalar() &&
168+
!llvm::has_single_bit<uint32_t>(QueryTy.getSizeInBits());
168169
};
169170
}
170171

@@ -184,14 +185,16 @@ LegalityPredicate LegalityPredicates::sameSize(unsigned TypeIdx0,
184185

185186
LegalityPredicate LegalityPredicates::memSizeInBytesNotPow2(unsigned MMOIdx) {
186187
return [=](const LegalityQuery &Query) {
187-
return !isPowerOf2_32(Query.MMODescrs[MMOIdx].MemoryTy.getSizeInBytes());
188+
return !llvm::has_single_bit<uint32_t>(
189+
Query.MMODescrs[MMOIdx].MemoryTy.getSizeInBytes());
188190
};
189191
}
190192

191193
LegalityPredicate LegalityPredicates::memSizeNotByteSizePow2(unsigned MMOIdx) {
192194
return [=](const LegalityQuery &Query) {
193195
const LLT MemTy = Query.MMODescrs[MMOIdx].MemoryTy;
194-
return !MemTy.isByteSized() || !isPowerOf2_32(MemTy.getSizeInBytes());
196+
return !MemTy.isByteSized() ||
197+
!llvm::has_single_bit<uint32_t>(MemTy.getSizeInBytes());
195198
};
196199
}
197200

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

+4-3
Original file line numberDiff line numberDiff line change
@@ -21526,9 +21526,10 @@ SDValue DAGCombiner::reduceBuildVecExtToExtBuildVec(SDNode *N) {
2152621526
// same source type and all of the inputs must be any or zero extend.
2152721527
// Scalar sizes must be a power of two.
2152821528
EVT OutScalarTy = VT.getScalarType();
21529-
bool ValidTypes = SourceType != MVT::Other &&
21530-
isPowerOf2_32(OutScalarTy.getSizeInBits()) &&
21531-
isPowerOf2_32(SourceType.getSizeInBits());
21529+
bool ValidTypes =
21530+
SourceType != MVT::Other &&
21531+
llvm::has_single_bit<uint32_t>(OutScalarTy.getSizeInBits()) &&
21532+
llvm::has_single_bit<uint32_t>(SourceType.getSizeInBits());
2153221533

2153321534
// Create a new simpler BUILD_VECTOR sequence which other optimizations can
2153421535
// turn into a single shuffle instruction.

‎llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -4272,7 +4272,7 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
42724272
// zero.
42734273
if (N0.getOpcode() == ISD::SRL && (C1.isZero() || C1.isOne()) &&
42744274
N0.getOperand(0).getOpcode() == ISD::CTLZ &&
4275-
isPowerOf2_32(N0.getScalarValueSizeInBits())) {
4275+
llvm::has_single_bit<uint32_t>(N0.getScalarValueSizeInBits())) {
42764276
if (ConstantSDNode *ShAmt = isConstOrConstSplat(N0.getOperand(1))) {
42774277
if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
42784278
ShAmt->getAPIntValue() == Log2_32(N0.getScalarValueSizeInBits())) {

‎llvm/lib/CodeGen/TargetLoweringBase.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -1626,7 +1626,7 @@ unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context,
16261626
if (EVT(DestVT).bitsLT(NewVT)) { // Value is expanded, e.g. i64 -> i16.
16271627
TypeSize NewVTSize = NewVT.getSizeInBits();
16281628
// Convert sizes such as i33 to i64.
1629-
if (!isPowerOf2_32(NewVTSize.getKnownMinValue()))
1629+
if (!llvm::has_single_bit<uint32_t>(NewVTSize.getKnownMinValue()))
16301630
NewVTSize = NewVTSize.coefficientNextPowerOf2();
16311631
return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
16321632
}

‎llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -6164,7 +6164,7 @@ AArch64InstructionSelector::selectExtendedSHL(
61646164
// Since we're going to pull this into a shift, the constant value must be
61656165
// a power of 2. If we got a multiply, then we need to check this.
61666166
if (OffsetOpc == TargetOpcode::G_MUL) {
6167-
if (!isPowerOf2_32(ImmVal))
6167+
if (!llvm::has_single_bit<uint32_t>(ImmVal))
61686168
return std::nullopt;
61696169

61706170
// Got a power of 2. So, the amount we'll shift is the log base-2 of that.

‎llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -981,8 +981,8 @@ bool AArch64LegalizerInfo::legalizeVectorTrunc(
981981
Register SrcReg = MI.getOperand(1).getReg();
982982
LLT DstTy = MRI.getType(DstReg);
983983
LLT SrcTy = MRI.getType(SrcReg);
984-
assert(isPowerOf2_32(DstTy.getSizeInBits()) &&
985-
isPowerOf2_32(SrcTy.getSizeInBits()));
984+
assert(llvm::has_single_bit<uint32_t>(DstTy.getSizeInBits()) &&
985+
llvm::has_single_bit<uint32_t>(SrcTy.getSizeInBits()));
986986

987987
// Split input type.
988988
LLT SplitSrcTy =

‎llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

+3-3
Original file line numberDiff line numberDiff line change
@@ -1580,7 +1580,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
15801580
const LLT &EltTy = Ty.getElementType();
15811581
if (EltTy.getSizeInBits() < 8 || EltTy.getSizeInBits() > 512)
15821582
return true;
1583-
if (!isPowerOf2_32(EltTy.getSizeInBits()))
1583+
if (!llvm::has_single_bit<uint32_t>(EltTy.getSizeInBits()))
15841584
return true;
15851585
}
15861586
return false;
@@ -1628,8 +1628,8 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
16281628
Builder.widenScalarIf(
16291629
[=](const LegalityQuery &Query) {
16301630
const LLT Ty = Query.Types[BigTyIdx];
1631-
return !isPowerOf2_32(Ty.getSizeInBits()) &&
1632-
Ty.getSizeInBits() % 16 != 0;
1631+
return !llvm::has_single_bit<uint32_t>(Ty.getSizeInBits()) &&
1632+
Ty.getSizeInBits() % 16 != 0;
16331633
},
16341634
[=](const LegalityQuery &Query) {
16351635
// Pick the next power of 2, or a multiple of 64 over 128.

‎llvm/lib/Target/ARM/ARMISelLowering.cpp

+4-4
Original file line numberDiff line numberDiff line change
@@ -14089,15 +14089,15 @@ static SDValue PerformMULCombine(SDNode *N,
1408914089
MulAmt >>= ShiftAmt;
1409014090

1409114091
if (MulAmt >= 0) {
14092-
if (isPowerOf2_32(MulAmt - 1)) {
14092+
if (llvm::has_single_bit<uint32_t>(MulAmt - 1)) {
1409314093
// (mul x, 2^N + 1) => (add (shl x, N), x)
1409414094
Res = DAG.getNode(ISD::ADD, DL, VT,
1409514095
V,
1409614096
DAG.getNode(ISD::SHL, DL, VT,
1409714097
V,
1409814098
DAG.getConstant(Log2_32(MulAmt - 1), DL,
1409914099
MVT::i32)));
14100-
} else if (isPowerOf2_32(MulAmt + 1)) {
14100+
} else if (llvm::has_single_bit<uint32_t>(MulAmt + 1)) {
1410114101
// (mul x, 2^N - 1) => (sub (shl x, N), x)
1410214102
Res = DAG.getNode(ISD::SUB, DL, VT,
1410314103
DAG.getNode(ISD::SHL, DL, VT,
@@ -14109,15 +14109,15 @@ static SDValue PerformMULCombine(SDNode *N,
1410914109
return SDValue();
1411014110
} else {
1411114111
uint64_t MulAmtAbs = -MulAmt;
14112-
if (isPowerOf2_32(MulAmtAbs + 1)) {
14112+
if (llvm::has_single_bit<uint32_t>(MulAmtAbs + 1)) {
1411314113
// (mul x, -(2^N - 1)) => (sub x, (shl x, N))
1411414114
Res = DAG.getNode(ISD::SUB, DL, VT,
1411514115
V,
1411614116
DAG.getNode(ISD::SHL, DL, VT,
1411714117
V,
1411814118
DAG.getConstant(Log2_32(MulAmtAbs + 1), DL,
1411914119
MVT::i32)));
14120-
} else if (isPowerOf2_32(MulAmtAbs - 1)) {
14120+
} else if (llvm::has_single_bit<uint32_t>(MulAmtAbs - 1)) {
1412114121
// (mul x, -(2^N + 1)) => - (add (shl x, N), x)
1412214122
Res = DAG.getNode(ISD::ADD, DL, VT,
1412314123
V,

‎llvm/lib/Target/AVR/AVRISelLowering.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -282,7 +282,7 @@ SDValue AVRTargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) const {
282282
const SDNode *N = Op.getNode();
283283
EVT VT = Op.getValueType();
284284
SDLoc dl(N);
285-
assert(isPowerOf2_32(VT.getSizeInBits()) &&
285+
assert(llvm::has_single_bit<uint32_t>(VT.getSizeInBits()) &&
286286
"Expected power-of-2 shift amount");
287287

288288
if (VT.getSizeInBits() == 32) {

‎llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp

+4-2
Original file line numberDiff line numberDiff line change
@@ -441,8 +441,10 @@ struct PPCOperand : public MCParsedAsmOperand {
441441

442442
bool isEvenRegNumber() const { return isRegNumber() && (getImm() & 1) == 0; }
443443

444-
bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
445-
isPowerOf2_32(getImm()); }
444+
bool isCRBitMask() const {
445+
return Kind == Immediate && isUInt<8>(getImm()) &&
446+
llvm::has_single_bit<uint32_t>(getImm());
447+
}
446448
bool isATBitsAsHint() const { return false; }
447449
bool isMem() const override { return false; }
448450
bool isReg() const override { return false; }

‎llvm/lib/Target/PowerPC/PPCISelLowering.cpp

+4-4
Original file line numberDiff line numberDiff line change
@@ -7843,15 +7843,15 @@ SDValue PPCTargetLowering::LowerTRUNCATEVector(SDValue Op,
78437843
EVT EltVT = TrgVT.getVectorElementType();
78447844
if (!isOperationCustom(Op.getOpcode(), TrgVT) ||
78457845
TrgVT.getSizeInBits() > 128 || !isPowerOf2_32(TrgNumElts) ||
7846-
!isPowerOf2_32(EltVT.getSizeInBits()))
7846+
!llvm::has_single_bit<uint32_t>(EltVT.getSizeInBits()))
78477847
return SDValue();
78487848

78497849
SDValue N1 = Op.getOperand(0);
78507850
EVT SrcVT = N1.getValueType();
78517851
unsigned SrcSize = SrcVT.getSizeInBits();
7852-
if (SrcSize > 256 ||
7853-
!isPowerOf2_32(SrcVT.getVectorNumElements()) ||
7854-
!isPowerOf2_32(SrcVT.getVectorElementType().getSizeInBits()))
7852+
if (SrcSize > 256 || !isPowerOf2_32(SrcVT.getVectorNumElements()) ||
7853+
!llvm::has_single_bit<uint32_t>(
7854+
SrcVT.getVectorElementType().getSizeInBits()))
78557855
return SDValue();
78567856
if (SrcSize == 256 && SrcVT.getVectorNumElements() < 2)
78577857
return SDValue();

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -9784,7 +9784,7 @@ static SDValue performBITREVERSECombine(SDNode *N, SelectionDAG &DAG,
97849784

97859785
EVT VT = N->getValueType(0);
97869786
if (!VT.isScalarInteger() || VT.getSizeInBits() >= Subtarget.getXLen() ||
9787-
!isPowerOf2_32(VT.getSizeInBits()))
9787+
!llvm::has_single_bit<uint32_t>(VT.getSizeInBits()))
97889788
return SDValue();
97899789

97909790
SDLoc DL(N);

‎llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

+3-3
Original file line numberDiff line numberDiff line change
@@ -2441,7 +2441,7 @@ void RISCVInstrInfo::getVLENFactoredAmount(MachineFunction &MF,
24412441
BuildMI(MBB, II, DL, get(RISCV::PseudoReadVLENB), DestReg).setMIFlag(Flag);
24422442
assert(isInt<32>(NumOfVReg) &&
24432443
"Expect the number of vector registers within 32-bits.");
2444-
if (isPowerOf2_32(NumOfVReg)) {
2444+
if (llvm::has_single_bit<uint32_t>(NumOfVReg)) {
24452445
uint32_t ShiftAmount = Log2_32(NumOfVReg);
24462446
if (ShiftAmount == 0)
24472447
return;
@@ -2477,7 +2477,7 @@ void RISCVInstrInfo::getVLENFactoredAmount(MachineFunction &MF,
24772477
.addReg(DestReg, RegState::Kill)
24782478
.addReg(DestReg)
24792479
.setMIFlag(Flag);
2480-
} else if (isPowerOf2_32(NumOfVReg - 1)) {
2480+
} else if (llvm::has_single_bit<uint32_t>(NumOfVReg - 1)) {
24812481
Register ScaledRegister = MRI.createVirtualRegister(&RISCV::GPRRegClass);
24822482
uint32_t ShiftAmount = Log2_32(NumOfVReg - 1);
24832483
BuildMI(MBB, II, DL, get(RISCV::SLLI), ScaledRegister)
@@ -2488,7 +2488,7 @@ void RISCVInstrInfo::getVLENFactoredAmount(MachineFunction &MF,
24882488
.addReg(ScaledRegister, RegState::Kill)
24892489
.addReg(DestReg, RegState::Kill)
24902490
.setMIFlag(Flag);
2491-
} else if (isPowerOf2_32(NumOfVReg + 1)) {
2491+
} else if (llvm::has_single_bit<uint32_t>(NumOfVReg + 1)) {
24922492
Register ScaledRegister = MRI.createVirtualRegister(&RISCV::GPRRegClass);
24932493
uint32_t ShiftAmount = Log2_32(NumOfVReg + 1);
24942494
BuildMI(MBB, II, DL, get(RISCV::SLLI), ScaledRegister)

‎llvm/lib/Target/RISCV/RISCVSubtarget.cpp

+2-1
Original file line numberDiff line numberDiff line change
@@ -158,7 +158,8 @@ unsigned RISCVSubtarget::getMinRVVVectorSizeInBits() const {
158158
unsigned RISCVSubtarget::getMaxLMULForFixedLengthVectors() const {
159159
assert(hasVInstructions() &&
160160
"Tried to get vector length without Zve or V extension support!");
161-
assert(RVVVectorLMULMax <= 8 && isPowerOf2_32(RVVVectorLMULMax) &&
161+
assert(RVVVectorLMULMax <= 8 &&
162+
llvm::has_single_bit<uint32_t>(RVVVectorLMULMax) &&
162163
"V extension requires a LMUL to be at most 8 and a power of 2!");
163164
return llvm::bit_floor(std::clamp<unsigned>(RVVVectorLMULMax, 1, 8));
164165
}

‎llvm/lib/Target/X86/X86ISelLowering.cpp

+6-4
Original file line numberDiff line numberDiff line change
@@ -24025,7 +24025,7 @@ static SDValue LowerVectorAllZero(const SDLoc &DL, SDValue V, ISD::CondCode CC,
2402524025
}
2402624026

2402724027
// Quit if not splittable to 128/256-bit vector.
24028-
if (!isPowerOf2_32(VT.getSizeInBits()))
24028+
if (!llvm::has_single_bit<uint32_t>(VT.getSizeInBits()))
2402924029
return SDValue();
2403024030

2403124031
// Split down to 128/256-bit vector.
@@ -24095,7 +24095,8 @@ static SDValue MatchVectorAllZeroTest(SDValue Op, ISD::CondCode CC,
2409524095
"Reduction source vector mismatch");
2409624096

2409724097
// Quit if less than 128-bits or not splittable to 128/256-bit vector.
24098-
if (VT.getSizeInBits() < 128 || !isPowerOf2_32(VT.getSizeInBits()))
24098+
if (VT.getSizeInBits() < 128 ||
24099+
!llvm::has_single_bit<uint32_t>(VT.getSizeInBits()))
2409924100
return SDValue();
2410024101

2410124102
// If more than one full vector is evaluated, OR them first before PTEST.
@@ -40361,9 +40362,10 @@ static SDValue combineX86ShufflesRecursively(
4036140362
// This function can be performance-critical, so we rely on the power-of-2
4036240363
// knowledge that we have about the mask sizes to replace div/rem ops with
4036340364
// bit-masks and shifts.
40364-
assert(isPowerOf2_32(RootMask.size()) &&
40365+
assert(llvm::has_single_bit<uint32_t>(RootMask.size()) &&
40366+
"Non-power-of-2 shuffle mask sizes");
40367+
assert(llvm::has_single_bit<uint32_t>(OpMask.size()) &&
4036540368
"Non-power-of-2 shuffle mask sizes");
40366-
assert(isPowerOf2_32(OpMask.size()) && "Non-power-of-2 shuffle mask sizes");
4036740369
unsigned RootMaskSizeLog2 = llvm::countr_zero(RootMask.size());
4036840370
unsigned OpMaskSizeLog2 = llvm::countr_zero(OpMask.size());
4036940371

‎llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -5010,7 +5010,7 @@ void BoUpSLP::buildTree_rec(ArrayRef<Value *> VL, unsigned Depth,
50105010
return isa<UndefValue>(V) ||
50115011
!isConstant(V);
50125012
})) ||
5013-
!llvm::isPowerOf2_32(NumUniqueScalarValues)) {
5013+
!llvm::has_single_bit<uint32_t>(NumUniqueScalarValues)) {
50145014
LLVM_DEBUG(dbgs() << "SLP: Scalar used twice in bundle.\n");
50155015
newTreeEntry(VL, std::nullopt /*not vectorized*/, S, UserTreeIdx);
50165016
return false;

‎llvm/utils/TableGen/DAGISelMatcherGen.cpp

+2-1
Original file line numberDiff line numberDiff line change
@@ -347,7 +347,8 @@ void MatcherGen::EmitOperatorMatchCode(const TreePatternNode *N,
347347
N->getChild(1)->isLeaf() && N->getChild(1)->getPredicateCalls().empty() &&
348348
N->getPredicateCalls().empty()) {
349349
if (IntInit *II = dyn_cast<IntInit>(N->getChild(1)->getLeafValue())) {
350-
if (!isPowerOf2_32(II->getValue())) { // Don't bother with single bits.
350+
if (!llvm::has_single_bit<uint32_t>(
351+
II->getValue())) { // Don't bother with single bits.
351352
// If this is at the root of the pattern, we emit a redundant
352353
// CheckOpcode so that the following checks get factored properly under
353354
// a single opcode check.

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