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[AArch64] Add some qshrn test cases. NFC
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‎llvm/test/CodeGen/AArch64/qshrn.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc %s -mtriple=aarch64 -o - | FileCheck %s
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define <4 x i16> @NarrowAShrI32By5(<4 x i32> %x) {
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; CHECK-LABEL: NarrowAShrI32By5:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sshr v0.4s, v0.4s, #5
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; CHECK-NEXT: sqxtn v0.4h, v0.4s
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; CHECK-NEXT: ret
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%s = ashr <4 x i32> %x, <i32 5, i32 5, i32 5, i32 5>
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%r = tail call <4 x i16> @llvm.aarch64.neon.sqxtn.v4i16(<4 x i32> %s)
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ret <4 x i16> %r
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}
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define <4 x i16> @NarrowAShrU32By5(<4 x i32> %x) {
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; CHECK-LABEL: NarrowAShrU32By5:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sshr v0.4s, v0.4s, #5
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; CHECK-NEXT: uqxtn v0.4h, v0.4s
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; CHECK-NEXT: ret
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%s = ashr <4 x i32> %x, <i32 5, i32 5, i32 5, i32 5>
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%r = tail call <4 x i16> @llvm.aarch64.neon.uqxtn.v4i16(<4 x i32> %s)
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ret <4 x i16> %r
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}
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define <4 x i16> @NarrowAShrI32By5ToU16(<4 x i32> %x) {
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; CHECK-LABEL: NarrowAShrI32By5ToU16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sshr v0.4s, v0.4s, #5
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; CHECK-NEXT: sqxtun v0.4h, v0.4s
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; CHECK-NEXT: ret
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%s = ashr <4 x i32> %x, <i32 5, i32 5, i32 5, i32 5>
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%r = tail call <4 x i16> @llvm.aarch64.neon.sqxtun.v4i16(<4 x i32> %s)
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ret <4 x i16> %r
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}
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define <4 x i16> @NarrowLShrI32By5(<4 x i32> %x) {
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; CHECK-LABEL: NarrowLShrI32By5:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ushr v0.4s, v0.4s, #5
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; CHECK-NEXT: sqxtn v0.4h, v0.4s
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; CHECK-NEXT: ret
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%s = lshr <4 x i32> %x, <i32 5, i32 5, i32 5, i32 5>
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%r = tail call <4 x i16> @llvm.aarch64.neon.sqxtn.v4i16(<4 x i32> %s)
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ret <4 x i16> %r
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}
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define <4 x i16> @NarrowLShrU32By5(<4 x i32> %x) {
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; CHECK-LABEL: NarrowLShrU32By5:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ushr v0.4s, v0.4s, #5
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; CHECK-NEXT: uqxtn v0.4h, v0.4s
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; CHECK-NEXT: ret
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%s = lshr <4 x i32> %x, <i32 5, i32 5, i32 5, i32 5>
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%r = tail call <4 x i16> @llvm.aarch64.neon.uqxtn.v4i16(<4 x i32> %s)
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ret <4 x i16> %r
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}
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define <4 x i16> @NarrowLShrI32By5ToU16(<4 x i32> %x) {
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; CHECK-LABEL: NarrowLShrI32By5ToU16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ushr v0.4s, v0.4s, #5
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; CHECK-NEXT: sqxtun v0.4h, v0.4s
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; CHECK-NEXT: ret
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%s = lshr <4 x i32> %x, <i32 5, i32 5, i32 5, i32 5>
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%r = tail call <4 x i16> @llvm.aarch64.neon.sqxtun.v4i16(<4 x i32> %s)
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ret <4 x i16> %r
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}
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define <2 x i32> @NarrowAShri64By5(<2 x i64> %x) {
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; CHECK-LABEL: NarrowAShri64By5:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sshr v0.2d, v0.2d, #5
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; CHECK-NEXT: sqxtn v0.2s, v0.2d
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; CHECK-NEXT: ret
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%s = ashr <2 x i64> %x, <i64 5, i64 5>
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%r = tail call <2 x i32> @llvm.aarch64.neon.sqxtn.v2i32(<2 x i64> %s)
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ret <2 x i32> %r
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}
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define <2 x i32> @NarrowAShrU64By5(<2 x i64> %x) {
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; CHECK-LABEL: NarrowAShrU64By5:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sshr v0.2d, v0.2d, #5
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; CHECK-NEXT: uqxtn v0.2s, v0.2d
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; CHECK-NEXT: ret
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%s = ashr <2 x i64> %x, <i64 5, i64 5>
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%r = tail call <2 x i32> @llvm.aarch64.neon.uqxtn.v2i32(<2 x i64> %s)
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ret <2 x i32> %r
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}
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define <2 x i32> @NarrowAShri64By5ToU32(<2 x i64> %x) {
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; CHECK-LABEL: NarrowAShri64By5ToU32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sshr v0.2d, v0.2d, #5
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; CHECK-NEXT: sqxtun v0.2s, v0.2d
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; CHECK-NEXT: ret
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%s = ashr <2 x i64> %x, <i64 5, i64 5>
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%r = tail call <2 x i32> @llvm.aarch64.neon.sqxtun.v2i32(<2 x i64> %s)
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ret <2 x i32> %r
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}
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define <2 x i32> @NarrowLShri64By5(<2 x i64> %x) {
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; CHECK-LABEL: NarrowLShri64By5:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ushr v0.2d, v0.2d, #5
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; CHECK-NEXT: sqxtn v0.2s, v0.2d
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; CHECK-NEXT: ret
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%s = lshr <2 x i64> %x, <i64 5, i64 5>
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%r = tail call <2 x i32> @llvm.aarch64.neon.sqxtn.v2i32(<2 x i64> %s)
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ret <2 x i32> %r
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}
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define <2 x i32> @NarrowLShrU64By5(<2 x i64> %x) {
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; CHECK-LABEL: NarrowLShrU64By5:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ushr v0.2d, v0.2d, #5
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; CHECK-NEXT: uqxtn v0.2s, v0.2d
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; CHECK-NEXT: ret
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%s = lshr <2 x i64> %x, <i64 5, i64 5>
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%r = tail call <2 x i32> @llvm.aarch64.neon.uqxtn.v2i32(<2 x i64> %s)
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ret <2 x i32> %r
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}
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define <2 x i32> @NarrowLShri64By5ToU32(<2 x i64> %x) {
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; CHECK-LABEL: NarrowLShri64By5ToU32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ushr v0.2d, v0.2d, #5
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; CHECK-NEXT: sqxtun v0.2s, v0.2d
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; CHECK-NEXT: ret
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%s = lshr <2 x i64> %x, <i64 5, i64 5>
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%r = tail call <2 x i32> @llvm.aarch64.neon.sqxtun.v2i32(<2 x i64> %s)
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ret <2 x i32> %r
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}
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define <8 x i8> @NarrowAShri16By5(<8 x i16> %x) {
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; CHECK-LABEL: NarrowAShri16By5:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sshr v0.8h, v0.8h, #5
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; CHECK-NEXT: sqxtn v0.8b, v0.8h
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; CHECK-NEXT: ret
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%s = ashr <8 x i16> %x, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
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%r = tail call <8 x i8> @llvm.aarch64.neon.sqxtn.v8i8(<8 x i16> %s)
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ret <8 x i8> %r
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}
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define <8 x i8> @NarrowAShrU16By5(<8 x i16> %x) {
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; CHECK-LABEL: NarrowAShrU16By5:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sshr v0.8h, v0.8h, #5
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; CHECK-NEXT: uqxtn v0.8b, v0.8h
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; CHECK-NEXT: ret
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%s = ashr <8 x i16> %x, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
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%r = tail call <8 x i8> @llvm.aarch64.neon.uqxtn.v8i8(<8 x i16> %s)
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ret <8 x i8> %r
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}
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define <8 x i8> @NarrowAShri16By5ToU8(<8 x i16> %x) {
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; CHECK-LABEL: NarrowAShri16By5ToU8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sshr v0.8h, v0.8h, #5
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; CHECK-NEXT: sqxtun v0.8b, v0.8h
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; CHECK-NEXT: ret
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%s = ashr <8 x i16> %x, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
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%r = tail call <8 x i8> @llvm.aarch64.neon.sqxtun.v8i8(<8 x i16> %s)
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ret <8 x i8> %r
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}
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define <8 x i8> @NarrowLShri16By5(<8 x i16> %x) {
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; CHECK-LABEL: NarrowLShri16By5:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ushr v0.8h, v0.8h, #5
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; CHECK-NEXT: sqxtn v0.8b, v0.8h
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; CHECK-NEXT: ret
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%s = lshr <8 x i16> %x, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
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%r = tail call <8 x i8> @llvm.aarch64.neon.sqxtn.v8i8(<8 x i16> %s)
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ret <8 x i8> %r
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}
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define <8 x i8> @NarrowLShrU16By5(<8 x i16> %x) {
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; CHECK-LABEL: NarrowLShrU16By5:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ushr v0.8h, v0.8h, #5
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; CHECK-NEXT: uqxtn v0.8b, v0.8h
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; CHECK-NEXT: ret
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%s = lshr <8 x i16> %x, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
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%r = tail call <8 x i8> @llvm.aarch64.neon.uqxtn.v8i8(<8 x i16> %s)
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ret <8 x i8> %r
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}
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define <8 x i8> @NarrowLShri16By5ToU8(<8 x i16> %x) {
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; CHECK-LABEL: NarrowLShri16By5ToU8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ushr v0.8h, v0.8h, #5
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; CHECK-NEXT: sqxtun v0.8b, v0.8h
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; CHECK-NEXT: ret
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%s = lshr <8 x i16> %x, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
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%r = tail call <8 x i8> @llvm.aarch64.neon.sqxtun.v8i8(<8 x i16> %s)
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ret <8 x i8> %r
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}
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define <4 x i16> @NarrowAShrI32By31(<4 x i32> %x) {
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; CHECK-LABEL: NarrowAShrI32By31:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sshr v0.4s, v0.4s, #16
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; CHECK-NEXT: sqxtn v0.4h, v0.4s
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; CHECK-NEXT: ret
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%s = ashr <4 x i32> %x, <i32 16, i32 16, i32 16, i32 16>
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%r = tail call <4 x i16> @llvm.aarch64.neon.sqxtn.v4i16(<4 x i32> %s)
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ret <4 x i16> %r
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}
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define <4 x i16> @NarrowAShrI32By31ToU16(<4 x i32> %x) {
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; CHECK-LABEL: NarrowAShrI32By31ToU16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sshr v0.4s, v0.4s, #16
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; CHECK-NEXT: sqxtun v0.4h, v0.4s
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; CHECK-NEXT: ret
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%s = ashr <4 x i32> %x, <i32 16, i32 16, i32 16, i32 16>
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%r = tail call <4 x i16> @llvm.aarch64.neon.sqxtun.v4i16(<4 x i32> %s)
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ret <4 x i16> %r
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}
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define <4 x i16> @NarrowLShrU32By31(<4 x i32> %x) {
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; CHECK-LABEL: NarrowLShrU32By31:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ushr v0.4s, v0.4s, #16
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; CHECK-NEXT: uqxtn v0.4h, v0.4s
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; CHECK-NEXT: ret
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%s = lshr <4 x i32> %x, <i32 16, i32 16, i32 16, i32 16>
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%r = tail call <4 x i16> @llvm.aarch64.neon.uqxtn.v4i16(<4 x i32> %s)
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ret <4 x i16> %r
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}
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define <16 x i8> @signed_minmax_v8i16_to_v16i8(<16 x i16> %x) {
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; CHECK-LABEL: signed_minmax_v8i16_to_v16i8:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: sshr v0.8h, v0.8h, #5
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; CHECK-NEXT: sshr v1.8h, v1.8h, #5
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; CHECK-NEXT: sqxtn v0.8b, v0.8h
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; CHECK-NEXT: sqxtn2 v0.16b, v1.8h
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; CHECK-NEXT: ret
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entry:
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%s = ashr <16 x i16> %x, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
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%min = call <16 x i16> @llvm.smin.v8i16(<16 x i16> %s, <16 x i16> <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>)
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%max = call <16 x i16> @llvm.smax.v8i16(<16 x i16> %min, <16 x i16> <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>)
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%trunc = trunc <16 x i16> %max to <16 x i8>
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ret <16 x i8> %trunc
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}
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define <16 x i8> @unsigned_minmax_v8i16_to_v16i8(<16 x i16> %x) {
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; CHECK-LABEL: unsigned_minmax_v8i16_to_v16i8:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: ushr v0.8h, v0.8h, #5
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; CHECK-NEXT: ushr v1.8h, v1.8h, #5
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; CHECK-NEXT: uqxtn v0.8b, v0.8h
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; CHECK-NEXT: uqxtn2 v0.16b, v1.8h
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; CHECK-NEXT: ret
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entry:
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%s = lshr <16 x i16> %x, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
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%min = call <16 x i16> @llvm.umin.v8i16(<16 x i16> %s, <16 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>)
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%trunc = trunc <16 x i16> %min to <16 x i8>
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ret <16 x i8> %trunc
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}
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define <16 x i8> @unsigned_signed_minmax_v8i16_to_v16i8(<16 x i16> %x) {
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; CHECK-LABEL: unsigned_signed_minmax_v8i16_to_v16i8:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: sshr v0.8h, v0.8h, #5
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; CHECK-NEXT: sshr v1.8h, v1.8h, #5
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; CHECK-NEXT: sqxtun v0.8b, v0.8h
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; CHECK-NEXT: sqxtun2 v0.16b, v1.8h
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; CHECK-NEXT: ret
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entry:
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%s = ashr <16 x i16> %x, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
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%max = call <16 x i16> @llvm.smax.v8i16(<16 x i16> %s, <16 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>)
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%min = call <16 x i16> @llvm.umin.v8i16(<16 x i16> %max, <16 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>)
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%trunc = trunc <16 x i16> %min to <16 x i8>
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ret <16 x i8> %trunc
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}
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define <8 x i16> @signed_minmax_v4i32_to_v8i16(<8 x i32> %x) {
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; CHECK-LABEL: signed_minmax_v4i32_to_v8i16:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: sshr v0.4s, v0.4s, #5
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; CHECK-NEXT: sshr v1.4s, v1.4s, #5
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; CHECK-NEXT: sqxtn v0.4h, v0.4s
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; CHECK-NEXT: sqxtn2 v0.8h, v1.4s
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; CHECK-NEXT: ret
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entry:
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%s = ashr <8 x i32> %x, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
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%min = call <8 x i32> @llvm.smin.v8i32(<8 x i32> %s, <8 x i32> <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767>)
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%max = call <8 x i32> @llvm.smax.v8i32(<8 x i32> %min, <8 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768>)
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%trunc = trunc <8 x i32> %max to <8 x i16>
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ret <8 x i16> %trunc
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}
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define <8 x i16> @unsigned_minmax_v4i32_to_v8i16(<8 x i32> %x) {
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; CHECK-LABEL: unsigned_minmax_v4i32_to_v8i16:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: ushr v0.4s, v0.4s, #5
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; CHECK-NEXT: ushr v1.4s, v1.4s, #5
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; CHECK-NEXT: uqxtn v0.4h, v0.4s
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; CHECK-NEXT: uqxtn2 v0.8h, v1.4s
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; CHECK-NEXT: ret
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entry:
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%s = lshr <8 x i32> %x, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
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%min = call <8 x i32> @llvm.umin.v8i32(<8 x i32> %s, <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>)
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%trunc = trunc <8 x i32> %min to <8 x i16>
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ret <8 x i16> %trunc
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}
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define <8 x i16> @unsigned_signed_minmax_v4i32_to_v8i16(<8 x i32> %x) {
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; CHECK-LABEL: unsigned_signed_minmax_v4i32_to_v8i16:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: sshr v0.4s, v0.4s, #5
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; CHECK-NEXT: sshr v1.4s, v1.4s, #5
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; CHECK-NEXT: sqxtun v0.4h, v0.4s
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; CHECK-NEXT: sqxtun2 v0.8h, v1.4s
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; CHECK-NEXT: ret
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entry:
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%s = ashr <8 x i32> %x, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
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%max = call <8 x i32> @llvm.smax.v8i32(<8 x i32> %s, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>)
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%min = call <8 x i32> @llvm.umin.v8i32(<8 x i32> %max, <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>)
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%trunc = trunc <8 x i32> %min to <8 x i16>
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ret <8 x i16> %trunc
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}
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define <4 x i32> @signed_minmax_v4i64_to_v8i32(<4 x i64> %x) {
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; CHECK-LABEL: signed_minmax_v4i64_to_v8i32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: sshr v0.2d, v0.2d, #5
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; CHECK-NEXT: sshr v1.2d, v1.2d, #5
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; CHECK-NEXT: sqxtn v0.2s, v0.2d
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; CHECK-NEXT: sqxtn2 v0.4s, v1.2d
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; CHECK-NEXT: ret
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entry:
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%s = ashr <4 x i64> %x, <i64 5, i64 5, i64 5, i64 5>
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%min = call <4 x i64> @llvm.smin.v8i64(<4 x i64> %s, <4 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>)
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%max = call <4 x i64> @llvm.smax.v8i64(<4 x i64> %min, <4 x i64> <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648>)
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%trunc = trunc <4 x i64> %max to <4 x i32>
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ret <4 x i32> %trunc
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}
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define <4 x i32> @unsigned_minmax_v4i64_to_v8i32(<4 x i64> %x) {
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; CHECK-LABEL: unsigned_minmax_v4i64_to_v8i32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: ushr v0.2d, v0.2d, #5
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; CHECK-NEXT: ushr v1.2d, v1.2d, #5
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; CHECK-NEXT: uqxtn v0.2s, v0.2d
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; CHECK-NEXT: uqxtn2 v0.4s, v1.2d
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; CHECK-NEXT: ret
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entry:
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%s = lshr <4 x i64> %x, <i64 5, i64 5, i64 5, i64 5>
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%min = call <4 x i64> @llvm.umin.v8i64(<4 x i64> %s, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>)
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%trunc = trunc <4 x i64> %min to <4 x i32>
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ret <4 x i32> %trunc
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}
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define <4 x i32> @unsigned_signed_minmax_v4i64_to_v8i32(<4 x i64> %x) {
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; CHECK-LABEL: unsigned_signed_minmax_v4i64_to_v8i32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: sshr v0.2d, v0.2d, #5
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; CHECK-NEXT: sshr v1.2d, v1.2d, #5
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; CHECK-NEXT: sqxtun v0.2s, v0.2d
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; CHECK-NEXT: sqxtun2 v0.4s, v1.2d
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; CHECK-NEXT: ret
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entry:
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%s = ashr <4 x i64> %x, <i64 5, i64 5, i64 5, i64 5>
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%max = call <4 x i64> @llvm.smax.v8i64(<4 x i64> %s, <4 x i64> <i64 0, i64 0, i64 0, i64 0>)
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%min = call <4 x i64> @llvm.umin.v8i64(<4 x i64> %max, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>)
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%trunc = trunc <4 x i64> %min to <4 x i32>
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ret <4 x i32> %trunc
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}

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