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1 | 1 | ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
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2 |
| -; RUN: opt < %s -passes=vector-combine -S -mtriple=x86_64-- -mattr=sse2 | FileCheck %s --check-prefixes=CHECK,SSE |
3 |
| -; RUN: opt < %s -passes=vector-combine -S -mtriple=x86_64-- -mattr=avx2 | FileCheck %s --check-prefixes=CHECK,AVX |
| 2 | +; RUN: opt < %s -passes=vector-combine -S -mtriple=x86_64-- -mattr=sse2 | FileCheck %s |
| 3 | +; RUN: opt < %s -passes=vector-combine -S -mtriple=x86_64-- -mattr=avx2 | FileCheck %s |
4 | 4 |
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5 | 5 | ; fold to identity
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6 | 6 |
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@@ -44,22 +44,17 @@ define <8 x i32> @concat_extract_subvectors_poison(<8 x i32> %x) {
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44 | 44 | ret <8 x i32> %concat
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45 | 45 | }
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46 | 46 |
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| 47 | +; broadcast loads are free on AVX (and blends are much cheap than general 2-operand shuffles) |
| 48 | + |
47 | 49 | define <4 x double> @blend_broadcasts_v4f64(ptr %p0, ptr %p1) {
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48 |
| -; SSE-LABEL: define <4 x double> @blend_broadcasts_v4f64( |
49 |
| -; SSE-SAME: ptr [[P0:%.*]], ptr [[P1:%.*]]) #[[ATTR0]] { |
50 |
| -; SSE-NEXT: [[LD0:%.*]] = load <4 x double>, ptr [[P0]], align 32 |
51 |
| -; SSE-NEXT: [[LD1:%.*]] = load <4 x double>, ptr [[P1]], align 32 |
52 |
| -; SSE-NEXT: [[BCST0:%.*]] = shufflevector <4 x double> [[LD0]], <4 x double> undef, <4 x i32> zeroinitializer |
53 |
| -; SSE-NEXT: [[BCST1:%.*]] = shufflevector <4 x double> [[LD1]], <4 x double> undef, <4 x i32> zeroinitializer |
54 |
| -; SSE-NEXT: [[BLEND:%.*]] = shufflevector <4 x double> [[BCST0]], <4 x double> [[BCST1]], <4 x i32> <i32 0, i32 5, i32 6, i32 3> |
55 |
| -; SSE-NEXT: ret <4 x double> [[BLEND]] |
56 |
| -; |
57 |
| -; AVX-LABEL: define <4 x double> @blend_broadcasts_v4f64( |
58 |
| -; AVX-SAME: ptr [[P0:%.*]], ptr [[P1:%.*]]) #[[ATTR0]] { |
59 |
| -; AVX-NEXT: [[LD0:%.*]] = load <4 x double>, ptr [[P0]], align 32 |
60 |
| -; AVX-NEXT: [[LD1:%.*]] = load <4 x double>, ptr [[P1]], align 32 |
61 |
| -; AVX-NEXT: [[BLEND:%.*]] = shufflevector <4 x double> [[LD0]], <4 x double> [[LD1]], <4 x i32> <i32 0, i32 4, i32 4, i32 0> |
62 |
| -; AVX-NEXT: ret <4 x double> [[BLEND]] |
| 50 | +; CHECK-LABEL: define <4 x double> @blend_broadcasts_v4f64( |
| 51 | +; CHECK-SAME: ptr [[P0:%.*]], ptr [[P1:%.*]]) #[[ATTR0]] { |
| 52 | +; CHECK-NEXT: [[LD0:%.*]] = load <4 x double>, ptr [[P0]], align 32 |
| 53 | +; CHECK-NEXT: [[LD1:%.*]] = load <4 x double>, ptr [[P1]], align 32 |
| 54 | +; CHECK-NEXT: [[BCST0:%.*]] = shufflevector <4 x double> [[LD0]], <4 x double> undef, <4 x i32> zeroinitializer |
| 55 | +; CHECK-NEXT: [[BCST1:%.*]] = shufflevector <4 x double> [[LD1]], <4 x double> undef, <4 x i32> zeroinitializer |
| 56 | +; CHECK-NEXT: [[BLEND:%.*]] = shufflevector <4 x double> [[BCST0]], <4 x double> [[BCST1]], <4 x i32> <i32 0, i32 5, i32 6, i32 3> |
| 57 | +; CHECK-NEXT: ret <4 x double> [[BLEND]] |
63 | 58 | ;
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64 | 59 | %ld0 = load <4 x double>, ptr %p0, align 32
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65 | 60 | %ld1 = load <4 x double>, ptr %p1, align 32
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