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[llvm][NFC] Use SDValue::getConstantOperandVal(i) where possible (#76708)
This helper function shortens examples like `cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();` to `Node->getConstantOperandVal(1);`. Implemented with: `git grep -l "cast<ConstantSDNode>\(.*->getOperand\(.*\)\)->getZExtValue\(\)" | xargs sed -E -i 's/cast<ConstantSDNode>\((.*)->getOperand\((.*)\)\)->getZExtValue\(\)/\1->getConstantOperandVal(\2)/` and `git grep -l "cast<ConstantSDNode>\(.*\.getOperand\(.*\)\)->getZExtValue\(\)" | xargs sed -E -i 's/cast<ConstantSDNode>\((.*)\.getOperand\((.*)\)\)->getZExtValue\(\)/\1.getConstantOperandVal(\2)/'`. With a couple of simple manual fixes needed. Result then processed by `git clang-format`.
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‎llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -495,7 +495,7 @@ void InstrEmitter::EmitSubregNode(SDNode *Node,
495495
// EXTRACT_SUBREG is lowered as %dst = COPY %src:sub. There are no
496496
// constraints on the %dst register, COPY can target all legal register
497497
// classes.
498-
unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
498+
unsigned SubIdx = Node->getConstantOperandVal(1);
499499
const TargetRegisterClass *TRC =
500500
TLI->getRegClassFor(Node->getSimpleValueType(0), Node->isDivergent());
501501

@@ -611,7 +611,7 @@ InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
611611
unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
612612

613613
// Create the new VReg in the destination class and emit a copy.
614-
unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
614+
unsigned DstRCIdx = Node->getConstantOperandVal(1);
615615
const TargetRegisterClass *DstRC =
616616
TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx));
617617
Register NewVReg = MRI->createVirtualRegister(DstRC);
@@ -629,7 +629,7 @@ InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
629629
void InstrEmitter::EmitRegSequence(SDNode *Node,
630630
DenseMap<SDValue, Register> &VRBaseMap,
631631
bool IsClone, bool IsCloned) {
632-
unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
632+
unsigned DstRCIdx = Node->getConstantOperandVal(0);
633633
const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
634634
Register NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC));
635635
const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
@@ -1309,8 +1309,7 @@ EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
13091309

13101310
// Add all of the operand registers to the instruction.
13111311
for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
1312-
unsigned Flags =
1313-
cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
1312+
unsigned Flags = Node->getConstantOperandVal(i);
13141313
const InlineAsm::Flag F(Flags);
13151314
const unsigned NumVals = F.getNumOperandRegisters();
13161315

‎llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -492,8 +492,7 @@ bool ScheduleDAGFast::DelayForLiveRegsBottomUp(SUnit *SU,
492492
--NumOps; // Ignore the glue operand.
493493

494494
for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
495-
unsigned Flags =
496-
cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
495+
unsigned Flags = Node->getConstantOperandVal(i);
497496
const InlineAsm::Flag F(Flags);
498497
unsigned NumVals = F.getNumOperandRegisters();
499498

‎llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -331,7 +331,7 @@ static void GetCostForDef(const ScheduleDAGSDNodes::RegDefIter &RegDefPos,
331331

332332
unsigned Opcode = Node->getMachineOpcode();
333333
if (Opcode == TargetOpcode::REG_SEQUENCE) {
334-
unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
334+
unsigned DstRCIdx = Node->getConstantOperandVal(0);
335335
const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
336336
RegClass = RC->getID();
337337
Cost = RegSequenceCost;
@@ -1369,8 +1369,7 @@ DelayForLiveRegsBottomUp(SUnit *SU, SmallVectorImpl<unsigned> &LRegs) {
13691369
--NumOps; // Ignore the glue operand.
13701370

13711371
for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
1372-
unsigned Flags =
1373-
cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
1372+
unsigned Flags = Node->getConstantOperandVal(i);
13741373
const InlineAsm::Flag F(Flags);
13751374
unsigned NumVals = F.getNumOperandRegisters();
13761375

@@ -2298,8 +2297,7 @@ void RegReductionPQBase::unscheduledNode(SUnit *SU) {
22982297
continue;
22992298
}
23002299
if (POpc == TargetOpcode::REG_SEQUENCE) {
2301-
unsigned DstRCIdx =
2302-
cast<ConstantSDNode>(PN->getOperand(0))->getZExtValue();
2300+
unsigned DstRCIdx = PN->getConstantOperandVal(0);
23032301
const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
23042302
unsigned RCId = RC->getID();
23052303
// REG_SEQUENCE is untyped, so getRepRegClassCostFor could not be used

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7408,7 +7408,7 @@ static bool isMemSrcFromConstant(SDValue Src, ConstantDataArraySlice &Slice) {
74087408
Src.getOperand(0).getOpcode() == ISD::GlobalAddress &&
74097409
Src.getOperand(1).getOpcode() == ISD::Constant) {
74107410
G = cast<GlobalAddressSDNode>(Src.getOperand(0));
7411-
SrcDelta = cast<ConstantSDNode>(Src.getOperand(1))->getZExtValue();
7411+
SrcDelta = Src.getConstantOperandVal(1);
74127412
}
74137413
if (!G)
74147414
return false;

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4181,8 +4181,7 @@ void SelectionDAGISel::CannotYetSelect(SDNode *N) {
41814181
Msg << "\nIn function: " << MF->getName();
41824182
} else {
41834183
bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
4184-
unsigned iid =
4185-
cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
4184+
unsigned iid = N->getConstantOperandVal(HasInputChain);
41864185
if (iid < Intrinsic::num_intrinsics)
41874186
Msg << "intrinsic %" << Intrinsic::getBaseName((Intrinsic::ID)iid);
41884187
else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())

‎llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

Lines changed: 17 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -1950,7 +1950,7 @@ void AArch64DAGToDAGISel::SelectMultiVectorMove(SDNode *N, unsigned NumVecs,
19501950
unsigned BaseReg, unsigned Op) {
19511951
unsigned TileNum = 0;
19521952
if (BaseReg != AArch64::ZA)
1953-
TileNum = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
1953+
TileNum = N->getConstantOperandVal(2);
19541954

19551955
if (!SelectSMETile(BaseReg, TileNum))
19561956
return;
@@ -2145,8 +2145,7 @@ void AArch64DAGToDAGISel::SelectLoadLane(SDNode *N, unsigned NumVecs,
21452145

21462146
const EVT ResTys[] = {MVT::Untyped, MVT::Other};
21472147

2148-
unsigned LaneNo =
2149-
cast<ConstantSDNode>(N->getOperand(NumVecs + 2))->getZExtValue();
2148+
unsigned LaneNo = N->getConstantOperandVal(NumVecs + 2);
21502149

21512150
SDValue Ops[] = {RegSeq, CurDAG->getTargetConstant(LaneNo, dl, MVT::i64),
21522151
N->getOperand(NumVecs + 3), N->getOperand(0)};
@@ -2185,8 +2184,7 @@ void AArch64DAGToDAGISel::SelectPostLoadLane(SDNode *N, unsigned NumVecs,
21852184
const EVT ResTys[] = {MVT::i64, // Type of the write back register
21862185
RegSeq->getValueType(0), MVT::Other};
21872186

2188-
unsigned LaneNo =
2189-
cast<ConstantSDNode>(N->getOperand(NumVecs + 1))->getZExtValue();
2187+
unsigned LaneNo = N->getConstantOperandVal(NumVecs + 1);
21902188

21912189
SDValue Ops[] = {RegSeq,
21922190
CurDAG->getTargetConstant(LaneNo, dl,
@@ -2237,8 +2235,7 @@ void AArch64DAGToDAGISel::SelectStoreLane(SDNode *N, unsigned NumVecs,
22372235

22382236
SDValue RegSeq = createQTuple(Regs);
22392237

2240-
unsigned LaneNo =
2241-
cast<ConstantSDNode>(N->getOperand(NumVecs + 2))->getZExtValue();
2238+
unsigned LaneNo = N->getConstantOperandVal(NumVecs + 2);
22422239

22432240
SDValue Ops[] = {RegSeq, CurDAG->getTargetConstant(LaneNo, dl, MVT::i64),
22442241
N->getOperand(NumVecs + 3), N->getOperand(0)};
@@ -2269,8 +2266,7 @@ void AArch64DAGToDAGISel::SelectPostStoreLane(SDNode *N, unsigned NumVecs,
22692266
const EVT ResTys[] = {MVT::i64, // Type of the write back register
22702267
MVT::Other};
22712268

2272-
unsigned LaneNo =
2273-
cast<ConstantSDNode>(N->getOperand(NumVecs + 1))->getZExtValue();
2269+
unsigned LaneNo = N->getConstantOperandVal(NumVecs + 1);
22742270

22752271
SDValue Ops[] = {RegSeq, CurDAG->getTargetConstant(LaneNo, dl, MVT::i64),
22762272
N->getOperand(NumVecs + 2), // Base Register
@@ -2576,8 +2572,8 @@ static bool isBitfieldExtractOp(SelectionDAG *CurDAG, SDNode *N, unsigned &Opc,
25762572
case AArch64::UBFMXri:
25772573
Opc = NOpc;
25782574
Opd0 = N->getOperand(0);
2579-
Immr = cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
2580-
Imms = cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
2575+
Immr = N->getConstantOperandVal(1);
2576+
Imms = N->getConstantOperandVal(2);
25812577
return true;
25822578
}
25832579
// Unreachable
@@ -3877,7 +3873,7 @@ bool AArch64DAGToDAGISel::tryWriteRegister(SDNode *N) {
38773873
assert(isa<ConstantSDNode>(N->getOperand(2)) &&
38783874
"Expected a constant integer expression.");
38793875
unsigned Reg = PMapper->Encoding;
3880-
uint64_t Immed = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
3876+
uint64_t Immed = N->getConstantOperandVal(2);
38813877
CurDAG->SelectNodeTo(
38823878
N, State, MVT::Other, CurDAG->getTargetConstant(Reg, DL, MVT::i32),
38833879
CurDAG->getTargetConstant(Immed, DL, MVT::i16), N->getOperand(0));
@@ -4173,8 +4169,7 @@ bool AArch64DAGToDAGISel::trySelectStackSlotTagP(SDNode *N) {
41734169

41744170
SDValue IRG_SP = N->getOperand(2);
41754171
if (IRG_SP->getOpcode() != ISD::INTRINSIC_W_CHAIN ||
4176-
cast<ConstantSDNode>(IRG_SP->getOperand(1))->getZExtValue() !=
4177-
Intrinsic::aarch64_irg_sp) {
4172+
IRG_SP->getConstantOperandVal(1) != Intrinsic::aarch64_irg_sp) {
41784173
return false;
41794174
}
41804175

@@ -4183,7 +4178,7 @@ bool AArch64DAGToDAGISel::trySelectStackSlotTagP(SDNode *N) {
41834178
int FI = cast<FrameIndexSDNode>(N->getOperand(1))->getIndex();
41844179
SDValue FiOp = CurDAG->getTargetFrameIndex(
41854180
FI, TLI->getPointerTy(CurDAG->getDataLayout()));
4186-
int TagOffset = cast<ConstantSDNode>(N->getOperand(3))->getZExtValue();
4181+
int TagOffset = N->getConstantOperandVal(3);
41874182

41884183
SDNode *Out = CurDAG->getMachineNode(
41894184
AArch64::TAGPstack, DL, MVT::i64,
@@ -4203,7 +4198,7 @@ void AArch64DAGToDAGISel::SelectTagP(SDNode *N) {
42034198

42044199
// General case for unrelated pointers in Op1 and Op2.
42054200
SDLoc DL(N);
4206-
int TagOffset = cast<ConstantSDNode>(N->getOperand(3))->getZExtValue();
4201+
int TagOffset = N->getConstantOperandVal(3);
42074202
SDNode *N1 = CurDAG->getMachineNode(AArch64::SUBP, DL, MVT::i64,
42084203
{N->getOperand(1), N->getOperand(2)});
42094204
SDNode *N2 = CurDAG->getMachineNode(AArch64::ADDXrr, DL, MVT::i64,
@@ -4219,7 +4214,7 @@ bool AArch64DAGToDAGISel::trySelectCastFixedLengthToScalableVector(SDNode *N) {
42194214
assert(N->getOpcode() == ISD::INSERT_SUBVECTOR && "Invalid Node!");
42204215

42214216
// Bail when not a "cast" like insert_subvector.
4222-
if (cast<ConstantSDNode>(N->getOperand(2))->getZExtValue() != 0)
4217+
if (N->getConstantOperandVal(2) != 0)
42234218
return false;
42244219
if (!N->getOperand(0).isUndef())
42254220
return false;
@@ -4250,7 +4245,7 @@ bool AArch64DAGToDAGISel::trySelectCastScalableToFixedLengthVector(SDNode *N) {
42504245
assert(N->getOpcode() == ISD::EXTRACT_SUBVECTOR && "Invalid Node!");
42514246

42524247
// Bail when not a "cast" like extract_subvector.
4253-
if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() != 0)
4248+
if (N->getConstantOperandVal(1) != 0)
42544249
return false;
42554250

42564251
// Bail when normal isel can do the job.
@@ -4422,7 +4417,7 @@ void AArch64DAGToDAGISel::Select(SDNode *Node) {
44224417
return;
44234418
}
44244419
case ISD::INTRINSIC_W_CHAIN: {
4425-
unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
4420+
unsigned IntNo = Node->getConstantOperandVal(1);
44264421
switch (IntNo) {
44274422
default:
44284423
break;
@@ -5179,7 +5174,7 @@ void AArch64DAGToDAGISel::Select(SDNode *Node) {
51795174
}
51805175
} break;
51815176
case ISD::INTRINSIC_WO_CHAIN: {
5182-
unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
5177+
unsigned IntNo = Node->getConstantOperandVal(0);
51835178
switch (IntNo) {
51845179
default:
51855180
break;
@@ -5782,7 +5777,7 @@ void AArch64DAGToDAGISel::Select(SDNode *Node) {
57825777
break;
57835778
}
57845779
case ISD::INTRINSIC_VOID: {
5785-
unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
5780+
unsigned IntNo = Node->getConstantOperandVal(1);
57865781
if (Node->getNumOperands() >= 3)
57875782
VT = Node->getOperand(2)->getValueType(0);
57885783
switch (IntNo) {
@@ -6806,7 +6801,7 @@ static EVT getMemVTFromNode(LLVMContext &Ctx, SDNode *Root) {
68066801
if (Opcode != ISD::INTRINSIC_VOID && Opcode != ISD::INTRINSIC_W_CHAIN)
68076802
return EVT();
68086803

6809-
switch (cast<ConstantSDNode>(Root->getOperand(1))->getZExtValue()) {
6804+
switch (Root->getConstantOperandVal(1)) {
68106805
default:
68116806
return EVT();
68126807
case Intrinsic::aarch64_sme_ldr:

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