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jmorsejmorse
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Revert "[NFC] Switch a number of DenseMaps to SmallDenseMaps for speedup (#109417)"
This reverts commit 3f37c51. Lo and behold, I missed a unit test
1 parent 3f37c51 commit 817e742

14 files changed

+101
-103
lines changed

‎llvm/include/llvm/Analysis/MemoryDependenceAnalysis.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -492,7 +492,7 @@ class MemoryDependenceResults {
492492
const MemoryLocation &Loc, bool isLoad,
493493
BasicBlock *BB,
494494
SmallVectorImpl<NonLocalDepResult> &Result,
495-
SmallDenseMap<BasicBlock *, Value *, 16> &Visited,
495+
DenseMap<BasicBlock *, Value *> &Visited,
496496
bool SkipFirstBlock = false,
497497
bool IsIncomplete = false);
498498
MemDepResult getNonLocalInfoForBlock(Instruction *QueryInst,

‎llvm/include/llvm/Analysis/SparsePropagation.h

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -87,9 +87,10 @@ template <class LatticeKey, class LatticeVal> class AbstractLatticeFunction {
8787
/// ComputeInstructionState - Compute the LatticeKeys that change as a result
8888
/// of executing instruction \p I. Their associated LatticeVals are store in
8989
/// \p ChangedValues.
90-
virtual void ComputeInstructionState(
91-
Instruction &I, SmallDenseMap<LatticeKey, LatticeVal, 16> &ChangedValues,
92-
SparseSolver<LatticeKey, LatticeVal> &SS) = 0;
90+
virtual void
91+
ComputeInstructionState(Instruction &I,
92+
DenseMap<LatticeKey, LatticeVal> &ChangedValues,
93+
SparseSolver<LatticeKey, LatticeVal> &SS) = 0;
9394

9495
/// PrintLatticeVal - Render the given LatticeVal to the specified stream.
9596
virtual void PrintLatticeVal(LatticeVal LV, raw_ostream &OS);
@@ -400,7 +401,7 @@ void SparseSolver<LatticeKey, LatticeVal, KeyInfo>::visitPHINode(PHINode &PN) {
400401
// computed from its incoming values. For example, SSI form stores its sigma
401402
// functions as PHINodes with a single incoming value.
402403
if (LatticeFunc->IsSpecialCasedPHI(&PN)) {
403-
SmallDenseMap<LatticeKey, LatticeVal, 16> ChangedValues;
404+
DenseMap<LatticeKey, LatticeVal> ChangedValues;
404405
LatticeFunc->ComputeInstructionState(PN, ChangedValues, *this);
405406
for (auto &ChangedValue : ChangedValues)
406407
if (ChangedValue.second != LatticeFunc->getUntrackedVal())
@@ -455,7 +456,7 @@ void SparseSolver<LatticeKey, LatticeVal, KeyInfo>::visitInst(Instruction &I) {
455456

456457
// Otherwise, ask the transfer function what the result is. If this is
457458
// something that we care about, remember it.
458-
SmallDenseMap<LatticeKey, LatticeVal, 16> ChangedValues;
459+
DenseMap<LatticeKey, LatticeVal> ChangedValues;
459460
LatticeFunc->ComputeInstructionState(I, ChangedValues, *this);
460461
for (auto &ChangedValue : ChangedValues)
461462
if (ChangedValue.second != LatticeFunc->getUntrackedVal())

‎llvm/lib/Analysis/MemoryDependenceAnalysis.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -888,7 +888,7 @@ void MemoryDependenceResults::getNonLocalPointerDependency(
888888
// each block. Because of critical edges, we currently bail out if querying
889889
// a block with multiple different pointers. This can happen during PHI
890890
// translation.
891-
SmallDenseMap<BasicBlock *, Value *, 16> Visited;
891+
DenseMap<BasicBlock *, Value *> Visited;
892892
if (getNonLocalPointerDepFromBB(QueryInst, Address, Loc, isLoad, FromBB,
893893
Result, Visited, true))
894894
return;
@@ -1038,7 +1038,7 @@ bool MemoryDependenceResults::getNonLocalPointerDepFromBB(
10381038
Instruction *QueryInst, const PHITransAddr &Pointer,
10391039
const MemoryLocation &Loc, bool isLoad, BasicBlock *StartBB,
10401040
SmallVectorImpl<NonLocalDepResult> &Result,
1041-
SmallDenseMap<BasicBlock *, Value *, 16> &Visited, bool SkipFirstBlock,
1041+
DenseMap<BasicBlock *, Value *> &Visited, bool SkipFirstBlock,
10421042
bool IsIncomplete) {
10431043
// Look up the cached info for Pointer.
10441044
ValueIsLoadPair CacheKey(Pointer.getAddr(), isLoad);

‎llvm/lib/Analysis/ScalarEvolution.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2255,7 +2255,7 @@ const SCEV *ScalarEvolution::getAnyExtendExpr(const SCEV *Op,
22552255
/// the common case where no interesting opportunities are present, and
22562256
/// is also used as a check to avoid infinite recursion.
22572257
static bool
2258-
CollectAddOperandsWithScales(SmallDenseMap<const SCEV *, APInt, 16> &M,
2258+
CollectAddOperandsWithScales(DenseMap<const SCEV *, APInt> &M,
22592259
SmallVectorImpl<const SCEV *> &NewOps,
22602260
APInt &AccumulatedConstant,
22612261
ArrayRef<const SCEV *> Ops, const APInt &Scale,
@@ -2753,7 +2753,7 @@ const SCEV *ScalarEvolution::getAddExpr(SmallVectorImpl<const SCEV *> &Ops,
27532753
// operands multiplied by constant values.
27542754
if (Idx < Ops.size() && isa<SCEVMulExpr>(Ops[Idx])) {
27552755
uint64_t BitWidth = getTypeSizeInBits(Ty);
2756-
SmallDenseMap<const SCEV *, APInt, 16> M;
2756+
DenseMap<const SCEV *, APInt> M;
27572757
SmallVector<const SCEV *, 8> NewOps;
27582758
APInt AccumulatedConstant(BitWidth, 0);
27592759
if (CollectAddOperandsWithScales(M, NewOps, AccumulatedConstant,

‎llvm/lib/CodeGen/CalcSpillWeights.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -222,7 +222,7 @@ float VirtRegAuxInfo::weightCalcHelper(LiveInterval &LI, SlotIndex *Start,
222222

223223
bool IsExiting = false;
224224
std::set<CopyHint> CopyHints;
225-
SmallDenseMap<unsigned, float, 8> Hint;
225+
DenseMap<unsigned, float> Hint;
226226
for (MachineRegisterInfo::reg_instr_nodbg_iterator
227227
I = MRI.reg_instr_nodbg_begin(LI.reg()),
228228
E = MRI.reg_instr_nodbg_end();

‎llvm/lib/CodeGen/MachineLICM.cpp

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -239,7 +239,7 @@ namespace {
239239

240240
bool IsCheapInstruction(MachineInstr &MI) const;
241241

242-
bool CanCauseHighRegPressure(const SmallDenseMap<unsigned, int> &Cost,
242+
bool CanCauseHighRegPressure(const DenseMap<unsigned, int> &Cost,
243243
bool Cheap);
244244

245245
void UpdateBackTraceRegPressure(const MachineInstr *MI);
@@ -264,9 +264,9 @@ namespace {
264264

265265
void InitRegPressure(MachineBasicBlock *BB);
266266

267-
SmallDenseMap<unsigned, int> calcRegisterCost(const MachineInstr *MI,
268-
bool ConsiderSeen,
269-
bool ConsiderUnseenAsDef);
267+
DenseMap<unsigned, int> calcRegisterCost(const MachineInstr *MI,
268+
bool ConsiderSeen,
269+
bool ConsiderUnseenAsDef);
270270

271271
void UpdateRegPressure(const MachineInstr *MI,
272272
bool ConsiderUnseenAsDef = false);
@@ -977,10 +977,10 @@ void MachineLICMImpl::UpdateRegPressure(const MachineInstr *MI,
977977
/// If 'ConsiderSeen' is true, updates 'RegSeen' and uses the information to
978978
/// figure out which usages are live-ins.
979979
/// FIXME: Figure out a way to consider 'RegSeen' from all code paths.
980-
SmallDenseMap<unsigned, int>
980+
DenseMap<unsigned, int>
981981
MachineLICMImpl::calcRegisterCost(const MachineInstr *MI, bool ConsiderSeen,
982982
bool ConsiderUnseenAsDef) {
983-
SmallDenseMap<unsigned, int> Cost;
983+
DenseMap<unsigned, int> Cost;
984984
if (MI->isImplicitDef())
985985
return Cost;
986986
for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
@@ -1248,7 +1248,7 @@ bool MachineLICMImpl::IsCheapInstruction(MachineInstr &MI) const {
12481248
/// Visit BBs from header to current BB, check if hoisting an instruction of the
12491249
/// given cost matrix can cause high register pressure.
12501250
bool MachineLICMImpl::CanCauseHighRegPressure(
1251-
const SmallDenseMap<unsigned, int> &Cost, bool CheapInstr) {
1251+
const DenseMap<unsigned, int> &Cost, bool CheapInstr) {
12521252
for (const auto &RPIdAndCost : Cost) {
12531253
if (RPIdAndCost.second <= 0)
12541254
continue;

‎llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp

Lines changed: 27 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -82,7 +82,8 @@ static unsigned countOperands(SDNode *Node, unsigned NumExpUses,
8282
/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
8383
/// implicit physical register output.
8484
void InstrEmitter::EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone,
85-
Register SrcReg, VRBaseMapType &VRBaseMap) {
85+
Register SrcReg,
86+
DenseMap<SDValue, Register> &VRBaseMap) {
8687
Register VRBase;
8788
if (SrcReg.isVirtual()) {
8889
// Just use the input register directly!
@@ -186,7 +187,7 @@ void InstrEmitter::CreateVirtualRegisters(SDNode *Node,
186187
MachineInstrBuilder &MIB,
187188
const MCInstrDesc &II,
188189
bool IsClone, bool IsCloned,
189-
VRBaseMapType &VRBaseMap) {
190+
DenseMap<SDValue, Register> &VRBaseMap) {
190191
assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
191192
"IMPLICIT_DEF should have been handled as a special case elsewhere!");
192193

@@ -264,7 +265,8 @@ void InstrEmitter::CreateVirtualRegisters(SDNode *Node,
264265

265266
/// getVR - Return the virtual register corresponding to the specified result
266267
/// of the specified node.
267-
Register InstrEmitter::getVR(SDValue Op, VRBaseMapType &VRBaseMap) {
268+
Register InstrEmitter::getVR(SDValue Op,
269+
DenseMap<SDValue, Register> &VRBaseMap) {
268270
if (Op.isMachineOpcode() &&
269271
Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
270272
// Add an IMPLICIT_DEF instruction before every use.
@@ -278,7 +280,7 @@ Register InstrEmitter::getVR(SDValue Op, VRBaseMapType &VRBaseMap) {
278280
return VReg;
279281
}
280282

281-
VRBaseMapType::iterator I = VRBaseMap.find(Op);
283+
DenseMap<SDValue, Register>::iterator I = VRBaseMap.find(Op);
282284
assert(I != VRBaseMap.end() && "Node emitted out of order - late");
283285
return I->second;
284286
}
@@ -316,7 +318,7 @@ InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
316318
SDValue Op,
317319
unsigned IIOpNum,
318320
const MCInstrDesc *II,
319-
VRBaseMapType &VRBaseMap,
321+
DenseMap<SDValue, Register> &VRBaseMap,
320322
bool IsDebug, bool IsClone, bool IsCloned) {
321323
assert(Op.getValueType() != MVT::Other &&
322324
Op.getValueType() != MVT::Glue &&
@@ -393,10 +395,12 @@ InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
393395
/// AddOperand - Add the specified operand to the specified machine instr. II
394396
/// specifies the instruction information for the node, and IIOpNum is the
395397
/// operand number (in the II) that we are adding.
396-
void InstrEmitter::AddOperand(MachineInstrBuilder &MIB, SDValue Op,
397-
unsigned IIOpNum, const MCInstrDesc *II,
398-
VRBaseMapType &VRBaseMap, bool IsDebug,
399-
bool IsClone, bool IsCloned) {
398+
void InstrEmitter::AddOperand(MachineInstrBuilder &MIB,
399+
SDValue Op,
400+
unsigned IIOpNum,
401+
const MCInstrDesc *II,
402+
DenseMap<SDValue, Register> &VRBaseMap,
403+
bool IsDebug, bool IsClone, bool IsCloned) {
400404
if (Op.isMachineOpcode()) {
401405
AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
402406
IsDebug, IsClone, IsCloned);
@@ -495,7 +499,8 @@ Register InstrEmitter::ConstrainForSubReg(Register VReg, unsigned SubIdx,
495499

496500
/// EmitSubregNode - Generate machine code for subreg nodes.
497501
///
498-
void InstrEmitter::EmitSubregNode(SDNode *Node, VRBaseMapType &VRBaseMap,
502+
void InstrEmitter::EmitSubregNode(SDNode *Node,
503+
DenseMap<SDValue, Register> &VRBaseMap,
499504
bool IsClone, bool IsCloned) {
500505
Register VRBase;
501506
unsigned Opc = Node->getMachineOpcode();
@@ -629,7 +634,7 @@ void InstrEmitter::EmitSubregNode(SDNode *Node, VRBaseMapType &VRBaseMap,
629634
///
630635
void
631636
InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
632-
VRBaseMapType &VRBaseMap) {
637+
DenseMap<SDValue, Register> &VRBaseMap) {
633638
Register VReg = getVR(Node->getOperand(0), VRBaseMap);
634639

635640
// Create the new VReg in the destination class and emit a copy.
@@ -648,8 +653,9 @@ InstrEmitter::EmitCopyToRegClassNode(SDNode *Node,
648653

649654
/// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes.
650655
///
651-
void InstrEmitter::EmitRegSequence(SDNode *Node, VRBaseMapType &VRBaseMap,
652-
bool IsClone, bool IsCloned) {
656+
void InstrEmitter::EmitRegSequence(SDNode *Node,
657+
DenseMap<SDValue, Register> &VRBaseMap,
658+
bool IsClone, bool IsCloned) {
653659
unsigned DstRCIdx = Node->getConstantOperandVal(0);
654660
const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
655661
Register NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC));
@@ -697,7 +703,7 @@ void InstrEmitter::EmitRegSequence(SDNode *Node, VRBaseMapType &VRBaseMap,
697703
///
698704
MachineInstr *
699705
InstrEmitter::EmitDbgValue(SDDbgValue *SD,
700-
VRBaseMapType &VRBaseMap) {
706+
DenseMap<SDValue, Register> &VRBaseMap) {
701707
DebugLoc DL = SD->getDebugLoc();
702708
assert(cast<DILocalVariable>(SD->getVariable())
703709
->isValidLocationForIntrinsic(DL) &&
@@ -749,7 +755,7 @@ MachineOperand GetMOForConstDbgOp(const SDDbgOperand &Op) {
749755
void InstrEmitter::AddDbgValueLocationOps(
750756
MachineInstrBuilder &MIB, const MCInstrDesc &DbgValDesc,
751757
ArrayRef<SDDbgOperand> LocationOps,
752-
VRBaseMapType &VRBaseMap) {
758+
DenseMap<SDValue, Register> &VRBaseMap) {
753759
for (const SDDbgOperand &Op : LocationOps) {
754760
switch (Op.getKind()) {
755761
case SDDbgOperand::FRAMEIX:
@@ -780,7 +786,7 @@ void InstrEmitter::AddDbgValueLocationOps(
780786

781787
MachineInstr *
782788
InstrEmitter::EmitDbgInstrRef(SDDbgValue *SD,
783-
VRBaseMapType &VRBaseMap) {
789+
DenseMap<SDValue, Register> &VRBaseMap) {
784790
MDNode *Var = SD->getVariable();
785791
const DIExpression *Expr = (DIExpression *)SD->getExpression();
786792
DebugLoc DL = SD->getDebugLoc();
@@ -856,7 +862,7 @@ InstrEmitter::EmitDbgInstrRef(SDDbgValue *SD,
856862
// Look up the corresponding VReg for the given SDNode, if any.
857863
SDNode *Node = DbgOperand.getSDNode();
858864
SDValue Op = SDValue(Node, DbgOperand.getResNo());
859-
VRBaseMapType::iterator I = VRBaseMap.find(Op);
865+
DenseMap<SDValue, Register>::iterator I = VRBaseMap.find(Op);
860866
// No VReg -> produce a DBG_VALUE $noreg instead.
861867
if (I == VRBaseMap.end())
862868
break;
@@ -922,7 +928,7 @@ MachineInstr *InstrEmitter::EmitDbgNoLocation(SDDbgValue *SD) {
922928

923929
MachineInstr *
924930
InstrEmitter::EmitDbgValueList(SDDbgValue *SD,
925-
VRBaseMapType &VRBaseMap) {
931+
DenseMap<SDValue, Register> &VRBaseMap) {
926932
MDNode *Var = SD->getVariable();
927933
DIExpression *Expr = SD->getExpression();
928934
DebugLoc DL = SD->getDebugLoc();
@@ -938,7 +944,7 @@ InstrEmitter::EmitDbgValueList(SDDbgValue *SD,
938944

939945
MachineInstr *
940946
InstrEmitter::EmitDbgValueFromSingleOp(SDDbgValue *SD,
941-
VRBaseMapType &VRBaseMap) {
947+
DenseMap<SDValue, Register> &VRBaseMap) {
942948
MDNode *Var = SD->getVariable();
943949
DIExpression *Expr = SD->getExpression();
944950
DebugLoc DL = SD->getDebugLoc();
@@ -990,7 +996,7 @@ InstrEmitter::EmitDbgLabel(SDDbgLabel *SD) {
990996
///
991997
void InstrEmitter::
992998
EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
993-
VRBaseMapType &VRBaseMap) {
999+
DenseMap<SDValue, Register> &VRBaseMap) {
9941000
unsigned Opc = Node->getMachineOpcode();
9951001

9961002
// Handle subreg insert/extract specially
@@ -1232,7 +1238,7 @@ EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned,
12321238
/// needed dependencies.
12331239
void InstrEmitter::
12341240
EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned,
1235-
VRBaseMapType &VRBaseMap) {
1241+
DenseMap<SDValue, Register> &VRBaseMap) {
12361242
switch (Node->getOpcode()) {
12371243
default:
12381244
#ifndef NDEBUG

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