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Revert "[RISCV] Store only VNInfo val no in VSETVLIInfo. NFC"
As noted in #93796 (comment), a better way to teach RISCVInsertVSETVLI to work without LiveIntervals is to set VNInfo to nullptr and teach the various methods to handle it. We should try that approach first, so we no longer need this pre-commit patch. This reverts commit 4b4d366.
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llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp

Lines changed: 14 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -504,7 +504,7 @@ DemandedFields getDemanded(const MachineInstr &MI, const RISCVSubtarget *ST) {
504504
class VSETVLIInfo {
505505
struct AVLDef {
506506
// Every AVLDef should have a VNInfo.
507-
unsigned ValNo;
507+
const VNInfo *ValNo;
508508
Register DefReg;
509509
};
510510
union {
@@ -543,9 +543,9 @@ class VSETVLIInfo {
543543
void setUnknown() { State = Unknown; }
544544
bool isUnknown() const { return State == Unknown; }
545545

546-
void setAVLRegDef(unsigned ValNo, Register AVLReg) {
547-
assert(AVLReg.isVirtual());
548-
AVLRegDef.ValNo = ValNo;
546+
void setAVLRegDef(const VNInfo *VNInfo, Register AVLReg) {
547+
assert(VNInfo && AVLReg.isVirtual());
548+
AVLRegDef.ValNo = VNInfo;
549549
AVLRegDef.DefReg = AVLReg;
550550
State = AVLIsReg;
551551
}
@@ -571,7 +571,7 @@ class VSETVLIInfo {
571571
assert(hasAVLImm());
572572
return AVLImm;
573573
}
574-
unsigned getAVLValNo() const {
574+
const VNInfo *getAVLVNInfo() const {
575575
assert(hasAVLReg());
576576
return AVLRegDef.ValNo;
577577
}
@@ -580,10 +580,8 @@ class VSETVLIInfo {
580580
// boundary slot.
581581
const MachineInstr *getAVLDefMI(const LiveIntervals *LIS) const {
582582
assert(hasAVLReg());
583-
const VNInfo *VNI =
584-
LIS->getInterval(getAVLReg()).getValNumInfo(getAVLValNo());
585-
auto *MI = LIS->getInstructionFromIndex(VNI->def);
586-
assert(!(VNI->isPHIDef() && MI));
583+
auto *MI = LIS->getInstructionFromIndex(getAVLVNInfo()->def);
584+
assert(!(getAVLVNInfo()->isPHIDef() && MI));
587585
return MI;
588586
}
589587

@@ -592,7 +590,7 @@ class VSETVLIInfo {
592590
if (Info.isUnknown())
593591
setUnknown();
594592
else if (Info.hasAVLReg())
595-
setAVLRegDef(Info.getAVLValNo(), Info.getAVLReg());
593+
setAVLRegDef(Info.getAVLVNInfo(), Info.getAVLReg());
596594
else if (Info.hasAVLVLMAX())
597595
setAVLVLMAX();
598596
else if (Info.hasAVLIgnored())
@@ -631,7 +629,7 @@ class VSETVLIInfo {
631629

632630
bool hasSameAVL(const VSETVLIInfo &Other) const {
633631
if (hasAVLReg() && Other.hasAVLReg())
634-
return getAVLValNo() == Other.getAVLValNo() &&
632+
return getAVLVNInfo()->id == Other.getAVLVNInfo()->id &&
635633
getAVLReg() == Other.getAVLReg();
636634

637635
if (hasAVLImm() && Other.hasAVLImm())
@@ -935,7 +933,7 @@ RISCVInsertVSETVLI::getInfoForVSETVLI(const MachineInstr &MI) const {
935933
if (AVLReg == RISCV::X0)
936934
NewInfo.setAVLVLMAX();
937935
else if (VNInfo *VNI = getVNInfoFromReg(AVLReg, MI, LIS))
938-
NewInfo.setAVLRegDef(VNI->id, AVLReg);
936+
NewInfo.setAVLRegDef(VNI, AVLReg);
939937
else {
940938
assert(MI.getOperand(1).isUndef());
941939
NewInfo.setAVLIgnored();
@@ -1011,7 +1009,7 @@ RISCVInsertVSETVLI::computeInfoForInstr(const MachineInstr &MI) const {
10111009
else
10121010
InstrInfo.setAVLImm(Imm);
10131011
} else if (VNInfo *VNI = getVNInfoFromReg(VLOp.getReg(), MI, LIS)) {
1014-
InstrInfo.setAVLRegDef(VNI->id, VLOp.getReg());
1012+
InstrInfo.setAVLRegDef(VNI, VLOp.getReg());
10151013
} else {
10161014
assert(VLOp.isUndef());
10171015
InstrInfo.setAVLIgnored();
@@ -1262,7 +1260,7 @@ void RISCVInsertVSETVLI::transferAfter(VSETVLIInfo &Info,
12621260
auto &LI = LIS->getInterval(MI.getOperand(1).getReg());
12631261
SlotIndex SI = LIS->getSlotIndexes()->getInstructionIndex(MI).getRegSlot();
12641262
VNInfo *VNI = LI.getVNInfoAt(SI);
1265-
Info.setAVLRegDef(VNI->id, MI.getOperand(1).getReg());
1263+
Info.setAVLRegDef(VNI, MI.getOperand(1).getReg());
12661264
return;
12671265
}
12681266

@@ -1357,8 +1355,7 @@ bool RISCVInsertVSETVLI::needVSETVLIPHI(const VSETVLIInfo &Require,
13571355
return true;
13581356

13591357
// We need the AVL to have been produced by a PHI node in this basic block.
1360-
const VNInfo *Valno = LIS->getInterval(Require.getAVLReg())
1361-
.getValNumInfo(Require.getAVLValNo());
1358+
const VNInfo *Valno = Require.getAVLVNInfo();
13621359
if (!Valno->isPHIDef() || LIS->getMBBFromIndex(Valno->def) != &MBB)
13631360
return true;
13641361

@@ -1522,8 +1519,7 @@ void RISCVInsertVSETVLI::doPRE(MachineBasicBlock &MBB) {
15221519
// we need to prove the value is available at the point we're going
15231520
// to insert the vsetvli at.
15241521
if (AvailableInfo.hasAVLReg()) {
1525-
const LiveInterval &LI = LIS->getInterval(AvailableInfo.getAVLReg());
1526-
SlotIndex SI = LI.getValNumInfo(AvailableInfo.getAVLValNo())->def;
1522+
SlotIndex SI = AvailableInfo.getAVLVNInfo()->def;
15271523
// This is an inline dominance check which covers the case of
15281524
// UnavailablePred being the preheader of a loop.
15291525
if (LIS->getMBBFromIndex(SI) != UnavailablePred)

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