@@ -504,7 +504,7 @@ DemandedFields getDemanded(const MachineInstr &MI, const RISCVSubtarget *ST) {
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class VSETVLIInfo {
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struct AVLDef {
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// Every AVLDef should have a VNInfo.
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- unsigned ValNo;
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+ const VNInfo * ValNo;
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Register DefReg;
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};
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union {
@@ -543,9 +543,9 @@ class VSETVLIInfo {
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void setUnknown () { State = Unknown; }
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bool isUnknown () const { return State == Unknown; }
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- void setAVLRegDef (unsigned ValNo , Register AVLReg) {
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- assert (AVLReg.isVirtual ());
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- AVLRegDef.ValNo = ValNo ;
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+ void setAVLRegDef (const VNInfo *VNInfo , Register AVLReg) {
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+ assert (VNInfo && AVLReg.isVirtual ());
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+ AVLRegDef.ValNo = VNInfo ;
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AVLRegDef.DefReg = AVLReg;
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State = AVLIsReg;
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}
@@ -571,7 +571,7 @@ class VSETVLIInfo {
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assert (hasAVLImm ());
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return AVLImm;
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}
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- unsigned getAVLValNo () const {
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+ const VNInfo * getAVLVNInfo () const {
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assert (hasAVLReg ());
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return AVLRegDef.ValNo ;
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}
@@ -580,10 +580,8 @@ class VSETVLIInfo {
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// boundary slot.
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const MachineInstr *getAVLDefMI (const LiveIntervals *LIS) const {
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assert (hasAVLReg ());
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- const VNInfo *VNI =
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- LIS->getInterval (getAVLReg ()).getValNumInfo (getAVLValNo ());
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- auto *MI = LIS->getInstructionFromIndex (VNI->def );
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- assert (!(VNI->isPHIDef () && MI));
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+ auto *MI = LIS->getInstructionFromIndex (getAVLVNInfo ()->def );
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+ assert (!(getAVLVNInfo ()->isPHIDef () && MI));
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return MI;
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}
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@@ -592,7 +590,7 @@ class VSETVLIInfo {
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if (Info.isUnknown ())
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setUnknown ();
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else if (Info.hasAVLReg ())
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- setAVLRegDef (Info.getAVLValNo (), Info.getAVLReg ());
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+ setAVLRegDef (Info.getAVLVNInfo (), Info.getAVLReg ());
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else if (Info.hasAVLVLMAX ())
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setAVLVLMAX ();
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else if (Info.hasAVLIgnored ())
@@ -631,7 +629,7 @@ class VSETVLIInfo {
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bool hasSameAVL (const VSETVLIInfo &Other) const {
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if (hasAVLReg () && Other.hasAVLReg ())
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- return getAVLValNo () == Other.getAVLValNo () &&
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+ return getAVLVNInfo ()-> id == Other.getAVLVNInfo ()-> id &&
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getAVLReg () == Other.getAVLReg ();
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if (hasAVLImm () && Other.hasAVLImm ())
@@ -935,7 +933,7 @@ RISCVInsertVSETVLI::getInfoForVSETVLI(const MachineInstr &MI) const {
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if (AVLReg == RISCV::X0)
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NewInfo.setAVLVLMAX ();
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else if (VNInfo *VNI = getVNInfoFromReg (AVLReg, MI, LIS))
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- NewInfo.setAVLRegDef (VNI-> id , AVLReg);
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+ NewInfo.setAVLRegDef (VNI, AVLReg);
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else {
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assert (MI.getOperand (1 ).isUndef ());
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NewInfo.setAVLIgnored ();
@@ -1011,7 +1009,7 @@ RISCVInsertVSETVLI::computeInfoForInstr(const MachineInstr &MI) const {
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else
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InstrInfo.setAVLImm (Imm);
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} else if (VNInfo *VNI = getVNInfoFromReg (VLOp.getReg (), MI, LIS)) {
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- InstrInfo.setAVLRegDef (VNI-> id , VLOp.getReg ());
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+ InstrInfo.setAVLRegDef (VNI, VLOp.getReg ());
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} else {
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assert (VLOp.isUndef ());
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InstrInfo.setAVLIgnored ();
@@ -1262,7 +1260,7 @@ void RISCVInsertVSETVLI::transferAfter(VSETVLIInfo &Info,
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auto &LI = LIS->getInterval (MI.getOperand (1 ).getReg ());
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SlotIndex SI = LIS->getSlotIndexes ()->getInstructionIndex (MI).getRegSlot ();
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VNInfo *VNI = LI.getVNInfoAt (SI);
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- Info.setAVLRegDef (VNI-> id , MI.getOperand (1 ).getReg ());
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+ Info.setAVLRegDef (VNI, MI.getOperand (1 ).getReg ());
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return ;
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}
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@@ -1357,8 +1355,7 @@ bool RISCVInsertVSETVLI::needVSETVLIPHI(const VSETVLIInfo &Require,
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return true ;
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// We need the AVL to have been produced by a PHI node in this basic block.
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- const VNInfo *Valno = LIS->getInterval (Require.getAVLReg ())
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- .getValNumInfo (Require.getAVLValNo ());
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+ const VNInfo *Valno = Require.getAVLVNInfo ();
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if (!Valno->isPHIDef () || LIS->getMBBFromIndex (Valno->def ) != &MBB)
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return true ;
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@@ -1522,8 +1519,7 @@ void RISCVInsertVSETVLI::doPRE(MachineBasicBlock &MBB) {
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// we need to prove the value is available at the point we're going
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// to insert the vsetvli at.
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if (AvailableInfo.hasAVLReg ()) {
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- const LiveInterval &LI = LIS->getInterval (AvailableInfo.getAVLReg ());
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- SlotIndex SI = LI.getValNumInfo (AvailableInfo.getAVLValNo ())->def ;
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+ SlotIndex SI = AvailableInfo.getAVLVNInfo ()->def ;
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// This is an inline dominance check which covers the case of
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// UnavailablePred being the preheader of a loop.
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if (LIS->getMBBFromIndex (SI) != UnavailablePred)
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