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[AArch64] Fix postinc operands for Neoverse-V1 scheduling
Similar to D159254, this fixes the order of WriteAdr operands on post/pre-inc loads/stores in the Neoverse-V1 scheduling model.
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-2115
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2 files changed

+2099
-2115
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‎llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td

+32-32
Original file line numberDiff line numberDiff line change
@@ -624,14 +624,14 @@ def : SchedAlias<WriteAdr, V1Write_1c_1I>;
624624
// Load pair, immed offset
625625
def : SchedAlias<WriteLDHi, V1Write_4c_1L>;
626626
def : InstRW<[V1Write_4c_1L, V1Write_0c_0Z], (instrs LDPWi, LDNPWi)>;
627-
def : InstRW<[V1Write_4c_1L, V1Write_0c_0Z, WriteAdr],
627+
def : InstRW<[WriteAdr, V1Write_4c_1L, V1Write_0c_0Z],
628628
(instrs LDPWpost, LDPWpre)>;
629629

630630
// Load pair, signed immed offset, signed words
631631
def : InstRW<[V1Write_5c_1I_1L, V1Write_0c_0Z], (instrs LDPSWi)>;
632632

633633
// Load pair, immed post or pre-index, signed words
634-
def : InstRW<[V1Write_5c_1I_1L, V1Write_0c_0Z, WriteAdr],
634+
def : InstRW<[WriteAdr, V1Write_5c_1I_1L, V1Write_0c_0Z],
635635
(instrs LDPSWpost, LDPSWpre)>;
636636

637637

@@ -735,7 +735,7 @@ def : InstRW<[V1Write_6c_1L, ReadAdrBase], (instregex "^LDR[SDQ]l$",
735735

736736
// Load vector reg, immed post-index
737737
// Load vector reg, immed pre-index
738-
def : InstRW<[V1Write_6c_1L, WriteAdr],
738+
def : InstRW<[WriteAdr, V1Write_6c_1L],
739739
(instregex "^LDR[BHSDQ](post|pre)$")>;
740740

741741
// Load vector reg, register offset, basic
@@ -756,12 +756,12 @@ def : InstRW<[V1Write_6c_1L, WriteLDHi], (instrs LDPQi, LDNPQi)>;
756756

757757
// Load vector pair, immed post-index, S/D-form
758758
// Load vector pair, immed pre-index, S/D-form
759-
def : InstRW<[V1Write_6c_1L, V1Write_0c_0Z, WriteAdr],
759+
def : InstRW<[WriteAdr, V1Write_6c_1L, V1Write_0c_0Z],
760760
(instregex "^LDP[SD](pre|post)$")>;
761761

762762
// Load vector pair, immed post-index, Q-form
763763
// Load vector pair, immed pre-index, Q-form
764-
def : InstRW<[V1Write_6c_1L, WriteLDHi, WriteAdr],
764+
def : InstRW<[WriteAdr, V1Write_6c_1L, WriteLDHi],
765765
(instrs LDPQpost, LDPQpre)>;
766766

767767

@@ -773,7 +773,7 @@ def : InstRW<[V1Write_2c_1L01_1V01], (instregex "^STUR[BHSDQ]i$")>;
773773

774774
// Store vector reg, immed post-index, B/H/S/D/Q-form
775775
// Store vector reg, immed pre-index, B/H/S/D/Q-form
776-
def : InstRW<[V1Write_2c_1L01_1V01, WriteAdr],
776+
def : InstRW<[WriteAdr, V1Write_2c_1L01_1V01],
777777
(instregex "^STR[BHSDQ](pre|post)$")>;
778778

779779
// Store vector reg, unsigned immed, B/H/S/D/Q-form
@@ -798,12 +798,12 @@ def : InstRW<[V1Write_2c_1L01_1V01], (instregex "^STN?P[SDQ]i$")>;
798798

799799
// Store vector pair, immed post-index, S/D-form
800800
// Store vector pair, immed pre-index, S/D-form
801-
def : InstRW<[V1Write_2c_1L01_1V01, WriteAdr],
801+
def : InstRW<[WriteAdr, V1Write_2c_1L01_1V01],
802802
(instregex "^STP[SD](pre|post)$")>;
803803

804804
// Store vector pair, immed post-index, Q-form
805805
// Store vector pair, immed pre-index, Q-form
806-
def : InstRW<[V1Write_2c_2L01_1V01, WriteAdr], (instrs STPQpre, STPQpost)>;
806+
def : InstRW<[WriteAdr, V1Write_2c_2L01_1V01], (instrs STPQpre, STPQpost)>;
807807

808808

809809
// ASIMD integer instructions
@@ -1074,60 +1074,60 @@ def : InstRW<[V1Write_5c_1M0_1V], (instregex "^INSvi(8|16|32|64)gpr$")>;
10741074
// ASIMD load, 1 element, multiple, 1 reg
10751075
def : InstRW<[V1Write_6c_1L],
10761076
(instregex "^LD1Onev(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
1077-
def : InstRW<[V1Write_6c_1L, WriteAdr],
1077+
def : InstRW<[WriteAdr, V1Write_6c_1L],
10781078
(instregex "^LD1Onev(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
10791079

10801080
// ASIMD load, 1 element, multiple, 2 reg
10811081
def : InstRW<[V1Write_6c_2L],
10821082
(instregex "^LD1Twov(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
1083-
def : InstRW<[V1Write_6c_2L, WriteAdr],
1083+
def : InstRW<[WriteAdr, V1Write_6c_2L],
10841084
(instregex "^LD1Twov(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
10851085

10861086
// ASIMD load, 1 element, multiple, 3 reg
10871087
def : InstRW<[V1Write_6c_3L],
10881088
(instregex "^LD1Threev(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
1089-
def : InstRW<[V1Write_6c_3L, WriteAdr],
1089+
def : InstRW<[WriteAdr, V1Write_6c_3L],
10901090
(instregex "^LD1Threev(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
10911091

10921092
// ASIMD load, 1 element, multiple, 4 reg, D-form
10931093
def : InstRW<[V1Write_6c_2L],
10941094
(instregex "^LD1Fourv(8b|4h|2s|1d)$")>;
1095-
def : InstRW<[V1Write_6c_2L, WriteAdr],
1095+
def : InstRW<[WriteAdr, V1Write_6c_2L],
10961096
(instregex "^LD1Fourv(8b|4h|2s|1d)_POST$")>;
10971097

10981098
// ASIMD load, 1 element, multiple, 4 reg, Q-form
10991099
def : InstRW<[V1Write_7c_4L],
11001100
(instregex "^LD1Fourv(16b|8h|4s|2d)$")>;
1101-
def : InstRW<[V1Write_7c_4L, WriteAdr],
1101+
def : InstRW<[WriteAdr, V1Write_7c_4L],
11021102
(instregex "^LD1Fourv(16b|8h|4s|2d)_POST$")>;
11031103

11041104
// ASIMD load, 1 element, one lane
11051105
// ASIMD load, 1 element, all lanes
11061106
def : InstRW<[V1Write_8c_1L_1V],
11071107
(instregex "^LD1(i|Rv)(8|16|32|64)$",
11081108
"^LD1Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
1109-
def : InstRW<[V1Write_8c_1L_1V, WriteAdr],
1109+
def : InstRW<[WriteAdr, V1Write_8c_1L_1V],
11101110
(instregex "^LD1i(8|16|32|64)_POST$",
11111111
"^LD1Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
11121112

11131113
// ASIMD load, 2 element, multiple, D-form
11141114
def : InstRW<[V1Write_8c_1L_2V],
11151115
(instregex "^LD2Twov(8b|4h|2s)$")>;
1116-
def : InstRW<[V1Write_8c_1L_2V, WriteAdr],
1116+
def : InstRW<[WriteAdr, V1Write_8c_1L_2V],
11171117
(instregex "^LD2Twov(8b|4h|2s)_POST$")>;
11181118

11191119
// ASIMD load, 2 element, multiple, Q-form
11201120
def : InstRW<[V1Write_8c_2L_2V],
11211121
(instregex "^LD2Twov(16b|8h|4s|2d)$")>;
1122-
def : InstRW<[V1Write_8c_2L_2V, WriteAdr],
1122+
def : InstRW<[WriteAdr, V1Write_8c_2L_2V],
11231123
(instregex "^LD2Twov(16b|8h|4s|2d)_POST$")>;
11241124

11251125
// ASIMD load, 2 element, one lane
11261126
// ASIMD load, 2 element, all lanes
11271127
def : InstRW<[V1Write_8c_1L_2V],
11281128
(instregex "^LD2i(8|16|32|64)$",
11291129
"^LD2Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
1130-
def : InstRW<[V1Write_8c_1L_2V, WriteAdr],
1130+
def : InstRW<[WriteAdr, V1Write_8c_1L_2V],
11311131
(instregex "^LD2i(8|16|32|64)_POST$",
11321132
"^LD2Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
11331133

@@ -1138,15 +1138,15 @@ def : InstRW<[V1Write_8c_2L_3V],
11381138
(instregex "^LD3Threev(8b|4h|2s)$",
11391139
"^LD3i(8|16|32|64)$",
11401140
"^LD3Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
1141-
def : InstRW<[V1Write_8c_2L_3V, WriteAdr],
1141+
def : InstRW<[WriteAdr, V1Write_8c_2L_3V],
11421142
(instregex "^LD3Threev(8b|4h|2s)_POST$",
11431143
"^LD3i(8|16|32|64)_POST$",
11441144
"^LD3Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
11451145

11461146
// ASIMD load, 3 element, multiple, Q-form
11471147
def : InstRW<[V1Write_8c_3L_3V],
11481148
(instregex "^LD3Threev(16b|8h|4s|2d)$")>;
1149-
def : InstRW<[V1Write_8c_3L_3V, WriteAdr],
1149+
def : InstRW<[WriteAdr, V1Write_8c_3L_3V],
11501150
(instregex "^LD3Threev(16b|8h|4s|2d)_POST$")>;
11511151

11521152
// ASIMD load, 4 element, multiple, D-form
@@ -1156,15 +1156,15 @@ def : InstRW<[V1Write_8c_3L_4V],
11561156
(instregex "^LD4Fourv(8b|4h|2s)$",
11571157
"^LD4i(8|16|32|64)$",
11581158
"^LD4Rv(8b|16b|4h|8h|2s|4s|1d|2d)$")>;
1159-
def : InstRW<[V1Write_8c_3L_4V, WriteAdr],
1159+
def : InstRW<[WriteAdr, V1Write_8c_3L_4V],
11601160
(instregex "^LD4Fourv(8b|4h|2s)_POST$",
11611161
"^LD4i(8|16|32|64)_POST$",
11621162
"^LD4Rv(8b|16b|4h|8h|2s|4s|1d|2d)_POST$")>;
11631163

11641164
// ASIMD load, 4 element, multiple, Q-form
11651165
def : InstRW<[V1Write_9c_4L_4V],
11661166
(instregex "^LD4Fourv(16b|8h|4s|2d)$")>;
1167-
def : InstRW<[V1Write_9c_4L_4V, WriteAdr],
1167+
def : InstRW<[WriteAdr, V1Write_9c_4L_4V],
11681168
(instregex "^LD4Fourv(16b|8h|4s|2d)_POST$")>;
11691169

11701170

@@ -1176,7 +1176,7 @@ def : InstRW<[V1Write_9c_4L_4V, WriteAdr],
11761176
def : InstRW<[V1Write_2c_1L01_1V01],
11771177
(instregex "^ST1Onev(8b|16b|4h|8h|2s|4s|1d|2d)$",
11781178
"^ST1Twov(8b|4h|2s|1d)$")>;
1179-
def : InstRW<[V1Write_2c_1L01_1V01, WriteAdr],
1179+
def : InstRW<[WriteAdr, V1Write_2c_1L01_1V01],
11801180
(instregex "^ST1Onev(8b|16b|4h|8h|2s|4s|1d|2d)_POST$",
11811181
"^ST1Twov(8b|4h|2s|1d)_POST$")>;
11821182

@@ -1187,21 +1187,21 @@ def : InstRW<[V1Write_2c_2L01_2V01],
11871187
(instregex "^ST1Twov(16b|8h|4s|2d)$",
11881188
"^ST1Threev(8b|4h|2s|1d)$",
11891189
"^ST1Fourv(8b|4h|2s|1d)$")>;
1190-
def : InstRW<[V1Write_2c_2L01_2V01, WriteAdr],
1190+
def : InstRW<[WriteAdr, V1Write_2c_2L01_2V01],
11911191
(instregex "^ST1Twov(16b|8h|4s|2d)_POST$",
11921192
"^ST1Threev(8b|4h|2s|1d)_POST$",
11931193
"^ST1Fourv(8b|4h|2s|1d)_POST$")>;
11941194

11951195
// ASIMD store, 1 element, multiple, 3 reg, Q-form
11961196
def : InstRW<[V1Write_2c_3L01_3V01],
11971197
(instregex "^ST1Threev(16b|8h|4s|2d)$")>;
1198-
def : InstRW<[V1Write_2c_3L01_3V01, WriteAdr],
1198+
def : InstRW<[WriteAdr, V1Write_2c_3L01_3V01],
11991199
(instregex "^ST1Threev(16b|8h|4s|2d)_POST$")>;
12001200

12011201
// ASIMD store, 1 element, multiple, 4 reg, Q-form
12021202
def : InstRW<[V1Write_2c_4L01_4V01],
12031203
(instregex "^ST1Fourv(16b|8h|4s|2d)$")>;
1204-
def : InstRW<[V1Write_2c_4L01_4V01, WriteAdr],
1204+
def : InstRW<[WriteAdr, V1Write_2c_4L01_4V01],
12051205
(instregex "^ST1Fourv(16b|8h|4s|2d)_POST$")>;
12061206

12071207
// ASIMD store, 1 element, one lane
@@ -1211,7 +1211,7 @@ def : InstRW<[V1Write_4c_1L01_1V01],
12111211
(instregex "^ST1i(8|16|32|64)$",
12121212
"^ST2Twov(8b|4h|2s)$",
12131213
"^ST2i(8|16|32|64)$")>;
1214-
def : InstRW<[V1Write_4c_1L01_1V01, WriteAdr],
1214+
def : InstRW<[WriteAdr, V1Write_4c_1L01_1V01],
12151215
(instregex "^ST1i(8|16|32|64)_POST$",
12161216
"^ST2Twov(8b|4h|2s)_POST$",
12171217
"^ST2i(8|16|32|64)_POST$")>;
@@ -1225,7 +1225,7 @@ def : InstRW<[V1Write_4c_2L01_2V01],
12251225
"^ST3Threev(8b|4h|2s)$",
12261226
"^ST3i(8|16|32|64)$",
12271227
"^ST4i64$")>;
1228-
def : InstRW<[V1Write_4c_2L01_2V01, WriteAdr],
1228+
def : InstRW<[WriteAdr, V1Write_4c_2L01_2V01],
12291229
(instregex "^ST2Twov(16b|8h|4s|2d)_POST$",
12301230
"^ST3Threev(8b|4h|2s)_POST$",
12311231
"^ST3i(8|16|32|64)_POST$",
@@ -1234,31 +1234,31 @@ def : InstRW<[V1Write_4c_2L01_2V01, WriteAdr],
12341234
// ASIMD store, 3 element, multiple, Q-form
12351235
def : InstRW<[V1Write_5c_3L01_3V01],
12361236
(instregex "^ST3Threev(16b|8h|4s|2d)$")>;
1237-
def : InstRW<[V1Write_5c_3L01_3V01, WriteAdr],
1237+
def : InstRW<[WriteAdr, V1Write_5c_3L01_3V01],
12381238
(instregex "^ST3Threev(16b|8h|4s|2d)_POST$")>;
12391239

12401240
// ASIMD store, 4 element, multiple, D-form
12411241
def : InstRW<[V1Write_6c_3L01_3V01],
12421242
(instregex "^ST4Fourv(8b|4h|2s)$")>;
1243-
def : InstRW<[V1Write_6c_3L01_3V01, WriteAdr],
1243+
def : InstRW<[WriteAdr, V1Write_6c_3L01_3V01],
12441244
(instregex "^ST4Fourv(8b|4h|2s)_POST$")>;
12451245

12461246
// ASIMD store, 4 element, multiple, Q-form, B/H/S
12471247
def : InstRW<[V1Write_7c_6L01_6V01],
12481248
(instregex "^ST4Fourv(16b|8h|4s)$")>;
1249-
def : InstRW<[V1Write_7c_6L01_6V01, WriteAdr],
1249+
def : InstRW<[WriteAdr, V1Write_7c_6L01_6V01],
12501250
(instregex "^ST4Fourv(16b|8h|4s)_POST$")>;
12511251

12521252
// ASIMD store, 4 element, multiple, Q-form, D
12531253
def : InstRW<[V1Write_4c_4L01_4V01],
12541254
(instrs ST4Fourv2d)>;
1255-
def : InstRW<[V1Write_4c_4L01_4V01, WriteAdr],
1255+
def : InstRW<[WriteAdr, V1Write_4c_4L01_4V01],
12561256
(instrs ST4Fourv2d_POST)>;
12571257

12581258
// ASIMD store, 4 element, one lane, B/H/S
12591259
def : InstRW<[V1Write_6c_3L_3V],
12601260
(instregex "^ST4i(8|16|32)$")>;
1261-
def : InstRW<[V1Write_6c_3L_3V, WriteAdr],
1261+
def : InstRW<[WriteAdr, V1Write_6c_3L_3V],
12621262
(instregex "^ST4i(8|16|32)_POST$")>;
12631263

12641264

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