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[RISCV] Strip W suffix from ADDIW (#68425)
The motivation of this change is simply to reduce test duplication. As can be seen in the (massive) test delta, we have many tests whose output differ only due to the use of addi on rv32 vs addiw on rv64 when the high bits are don't care. As an aside, we don't need to worry about the non-zero immediate restriction on the compressed variants because we're not directly forming the compressed variants. If we happen to get a zero immediate for the ADDI, then either a later optimization will strip the useless instruction or the encoder is responsible for not compressing the instruction.
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107 files changed

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‎llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp

Lines changed: 9 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -12,11 +12,14 @@
1212
// extended bits aren't consumed or because the input was already sign extended
1313
// by an earlier instruction.
1414
//
15-
// Then it removes the -w suffix from addw, slliw and mulw instructions
16-
// whenever all users are dependent only on the lower word of the result of the
17-
// instruction. We do this only for addw, slliw, and mulw because the -w forms
18-
// are less compressible: c.add and c.slli have a larger register encoding than
19-
// their w counterparts, and there's no compressible version of mulw.
15+
// Then it removes the -w suffix from opw instructions whenever all users are
16+
// dependent only on the lower word of the result of the instruction.
17+
// The cases handled are:
18+
// * addw because c.add has a larger register encoding than c.addw.
19+
// * addiw because it helps reduce test differences between RV32 and RV64
20+
// w/o being a pessimization.
21+
// * mulw because c.mulw doesn't exist but c.mul does (w/ zcb)
22+
// * slliw because c.slliw doesn't exist and c.slli does
2023
//
2124
//===---------------------------------------------------------------------===//
2225

@@ -661,6 +664,7 @@ bool RISCVOptWInstrs::stripWSuffixes(MachineFunction &MF,
661664
default:
662665
continue;
663666
case RISCV::ADDW: Opc = RISCV::ADD; break;
667+
case RISCV::ADDIW: Opc = RISCV::ADDI; break;
664668
case RISCV::MULW: Opc = RISCV::MUL; break;
665669
case RISCV::SLLIW: Opc = RISCV::SLLI; break;
666670
}

‎llvm/test/CodeGen/RISCV/add-before-shl.ll

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,7 @@ define signext i32 @add_small_const(i32 signext %a) nounwind {
2525
;
2626
; RV64I-LABEL: add_small_const:
2727
; RV64I: # %bb.0:
28-
; RV64I-NEXT: addiw a0, a0, 1
28+
; RV64I-NEXT: addi a0, a0, 1
2929
; RV64I-NEXT: slli a0, a0, 56
3030
; RV64I-NEXT: srai a0, a0, 56
3131
; RV64I-NEXT: jalr zero, 0(ra)
@@ -39,7 +39,7 @@ define signext i32 @add_small_const(i32 signext %a) nounwind {
3939
;
4040
; RV64C-LABEL: add_small_const:
4141
; RV64C: # %bb.0:
42-
; RV64C-NEXT: c.addiw a0, 1
42+
; RV64C-NEXT: c.addi a0, 1
4343
; RV64C-NEXT: c.slli a0, 56
4444
; RV64C-NEXT: c.srai a0, 56
4545
; RV64C-NEXT: c.jr ra
@@ -78,7 +78,7 @@ define signext i32 @add_large_const(i32 signext %a) nounwind {
7878
; RV64C-LABEL: add_large_const:
7979
; RV64C: # %bb.0:
8080
; RV64C-NEXT: c.lui a1, 1
81-
; RV64C-NEXT: c.addiw a1, -1
81+
; RV64C-NEXT: c.addi a1, -1
8282
; RV64C-NEXT: c.add a0, a1
8383
; RV64C-NEXT: c.slli a0, 48
8484
; RV64C-NEXT: c.srai a0, 48
@@ -118,7 +118,7 @@ define signext i32 @add_huge_const(i32 signext %a) nounwind {
118118
; RV64C-LABEL: add_huge_const:
119119
; RV64C: # %bb.0:
120120
; RV64C-NEXT: c.lui a1, 8
121-
; RV64C-NEXT: c.addiw a1, -1
121+
; RV64C-NEXT: c.addi a1, -1
122122
; RV64C-NEXT: c.add a0, a1
123123
; RV64C-NEXT: c.slli a0, 48
124124
; RV64C-NEXT: c.srai a0, 48
@@ -139,7 +139,7 @@ define signext i24 @add_non_machine_type(i24 signext %a) nounwind {
139139
;
140140
; RV64I-LABEL: add_non_machine_type:
141141
; RV64I: # %bb.0:
142-
; RV64I-NEXT: addiw a0, a0, 256
142+
; RV64I-NEXT: addi a0, a0, 256
143143
; RV64I-NEXT: slli a0, a0, 52
144144
; RV64I-NEXT: srai a0, a0, 40
145145
; RV64I-NEXT: jalr zero, 0(ra)
@@ -153,7 +153,7 @@ define signext i24 @add_non_machine_type(i24 signext %a) nounwind {
153153
;
154154
; RV64C-LABEL: add_non_machine_type:
155155
; RV64C: # %bb.0:
156-
; RV64C-NEXT: addiw a0, a0, 256
156+
; RV64C-NEXT: addi a0, a0, 256
157157
; RV64C-NEXT: c.slli a0, 52
158158
; RV64C-NEXT: c.srai a0, 40
159159
; RV64C-NEXT: c.jr ra

‎llvm/test/CodeGen/RISCV/add-imm.ll

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@ define i32 @add_positive_low_bound_accept(i32 %a) nounwind {
2929
;
3030
; RV64I-LABEL: add_positive_low_bound_accept:
3131
; RV64I: # %bb.0:
32-
; RV64I-NEXT: addiw a0, a0, 2047
32+
; RV64I-NEXT: addi a0, a0, 2047
3333
; RV64I-NEXT: addiw a0, a0, 1
3434
; RV64I-NEXT: ret
3535
%1 = add i32 %a, 2048
@@ -45,7 +45,7 @@ define i32 @add_positive_high_bound_accept(i32 %a) nounwind {
4545
;
4646
; RV64I-LABEL: add_positive_high_bound_accept:
4747
; RV64I: # %bb.0:
48-
; RV64I-NEXT: addiw a0, a0, 2047
48+
; RV64I-NEXT: addi a0, a0, 2047
4949
; RV64I-NEXT: addiw a0, a0, 2047
5050
; RV64I-NEXT: ret
5151
%1 = add i32 %a, 4094
@@ -63,7 +63,7 @@ define i32 @add_positive_high_bound_reject(i32 %a) nounwind {
6363
; RV64I-LABEL: add_positive_high_bound_reject:
6464
; RV64I: # %bb.0:
6565
; RV64I-NEXT: lui a1, 1
66-
; RV64I-NEXT: addiw a1, a1, -1
66+
; RV64I-NEXT: addi a1, a1, -1
6767
; RV64I-NEXT: addw a0, a0, a1
6868
; RV64I-NEXT: ret
6969
%1 = add i32 %a, 4095
@@ -93,7 +93,7 @@ define i32 @add_negative_high_bound_accept(i32 %a) nounwind {
9393
;
9494
; RV64I-LABEL: add_negative_high_bound_accept:
9595
; RV64I: # %bb.0:
96-
; RV64I-NEXT: addiw a0, a0, -2048
96+
; RV64I-NEXT: addi a0, a0, -2048
9797
; RV64I-NEXT: addiw a0, a0, -1
9898
; RV64I-NEXT: ret
9999
%1 = add i32 %a, -2049
@@ -109,7 +109,7 @@ define i32 @add_negative_low_bound_accept(i32 %a) nounwind {
109109
;
110110
; RV64I-LABEL: add_negative_low_bound_accept:
111111
; RV64I: # %bb.0:
112-
; RV64I-NEXT: addiw a0, a0, -2048
112+
; RV64I-NEXT: addi a0, a0, -2048
113113
; RV64I-NEXT: addiw a0, a0, -2048
114114
; RV64I-NEXT: ret
115115
%1 = add i32 %a, -4096
@@ -127,7 +127,7 @@ define i32 @add_negative_low_bound_reject(i32 %a) nounwind {
127127
; RV64I-LABEL: add_negative_low_bound_reject:
128128
; RV64I: # %bb.0:
129129
; RV64I-NEXT: lui a1, 1048575
130-
; RV64I-NEXT: addiw a1, a1, -1
130+
; RV64I-NEXT: addi a1, a1, -1
131131
; RV64I-NEXT: addw a0, a0, a1
132132
; RV64I-NEXT: ret
133133
%1 = add i32 %a, -4097
@@ -143,7 +143,7 @@ define i32 @add32_accept(i32 %a) nounwind {
143143
;
144144
; RV64I-LABEL: add32_accept:
145145
; RV64I: # %bb.0:
146-
; RV64I-NEXT: addiw a0, a0, 2047
146+
; RV64I-NEXT: addi a0, a0, 2047
147147
; RV64I-NEXT: addiw a0, a0, 952
148148
; RV64I-NEXT: ret
149149
%1 = add i32 %a, 2999
@@ -159,7 +159,7 @@ define signext i32 @add32_sext_accept(i32 signext %a) nounwind {
159159
;
160160
; RV64I-LABEL: add32_sext_accept:
161161
; RV64I: # %bb.0:
162-
; RV64I-NEXT: addiw a0, a0, 2047
162+
; RV64I-NEXT: addi a0, a0, 2047
163163
; RV64I-NEXT: addiw a0, a0, 952
164164
; RV64I-NEXT: ret
165165
%1 = add i32 %a, 2999
@@ -178,7 +178,7 @@ define signext i32 @add32_sext_reject_on_rv64(i32 signext %a) nounwind {
178178
;
179179
; RV64I-LABEL: add32_sext_reject_on_rv64:
180180
; RV64I: # %bb.0:
181-
; RV64I-NEXT: addiw a0, a0, 2047
181+
; RV64I-NEXT: addi a0, a0, 2047
182182
; RV64I-NEXT: addiw a0, a0, 953
183183
; RV64I-NEXT: lui a1, %hi(gv0)
184184
; RV64I-NEXT: sw a0, %lo(gv0)(a1)
@@ -231,7 +231,7 @@ define void @add32_reject() nounwind {
231231
; RV64I-NEXT: lui a2, %hi(gb)
232232
; RV64I-NEXT: lw a3, %lo(gb)(a2)
233233
; RV64I-NEXT: lui a4, 1
234-
; RV64I-NEXT: addiw a4, a4, -1096
234+
; RV64I-NEXT: addi a4, a4, -1096
235235
; RV64I-NEXT: add a1, a1, a4
236236
; RV64I-NEXT: add a3, a3, a4
237237
; RV64I-NEXT: sw a1, %lo(ga)(a0)

‎llvm/test/CodeGen/RISCV/addimm-mulimm.ll

Lines changed: 28 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -84,7 +84,7 @@ define i32 @add_mul_combine_accept_b1(i32 %x) {
8484
; RV64IMB-NEXT: li a1, 23
8585
; RV64IMB-NEXT: mul a0, a0, a1
8686
; RV64IMB-NEXT: lui a1, 50
87-
; RV64IMB-NEXT: addiw a1, a1, 1119
87+
; RV64IMB-NEXT: addi a1, a1, 1119
8888
; RV64IMB-NEXT: addw a0, a0, a1
8989
; RV64IMB-NEXT: ret
9090
%tmp0 = add i32 %x, 8953
@@ -107,7 +107,7 @@ define signext i32 @add_mul_combine_accept_b2(i32 signext %x) {
107107
; RV64IMB-NEXT: li a1, 23
108108
; RV64IMB-NEXT: mul a0, a0, a1
109109
; RV64IMB-NEXT: lui a1, 50
110-
; RV64IMB-NEXT: addiw a1, a1, 1119
110+
; RV64IMB-NEXT: addi a1, a1, 1119
111111
; RV64IMB-NEXT: addw a0, a0, a1
112112
; RV64IMB-NEXT: ret
113113
%tmp0 = add i32 %x, 8953
@@ -153,7 +153,7 @@ define i32 @add_mul_combine_reject_a1(i32 %x) {
153153
;
154154
; RV64IMB-LABEL: add_mul_combine_reject_a1:
155155
; RV64IMB: # %bb.0:
156-
; RV64IMB-NEXT: addiw a0, a0, 1971
156+
; RV64IMB-NEXT: addi a0, a0, 1971
157157
; RV64IMB-NEXT: li a1, 29
158158
; RV64IMB-NEXT: mulw a0, a0, a1
159159
; RV64IMB-NEXT: ret
@@ -172,7 +172,7 @@ define signext i32 @add_mul_combine_reject_a2(i32 signext %x) {
172172
;
173173
; RV64IMB-LABEL: add_mul_combine_reject_a2:
174174
; RV64IMB: # %bb.0:
175-
; RV64IMB-NEXT: addiw a0, a0, 1971
175+
; RV64IMB-NEXT: addi a0, a0, 1971
176176
; RV64IMB-NEXT: li a1, 29
177177
; RV64IMB-NEXT: mulw a0, a0, a1
178178
; RV64IMB-NEXT: ret
@@ -217,7 +217,7 @@ define i32 @add_mul_combine_reject_c1(i32 %x) {
217217
;
218218
; RV64IMB-LABEL: add_mul_combine_reject_c1:
219219
; RV64IMB: # %bb.0:
220-
; RV64IMB-NEXT: addiw a0, a0, 1000
220+
; RV64IMB-NEXT: addi a0, a0, 1000
221221
; RV64IMB-NEXT: sh3add a1, a0, a0
222222
; RV64IMB-NEXT: sh3add a0, a1, a0
223223
; RV64IMB-NEXT: sext.w a0, a0
@@ -237,7 +237,7 @@ define signext i32 @add_mul_combine_reject_c2(i32 signext %x) {
237237
;
238238
; RV64IMB-LABEL: add_mul_combine_reject_c2:
239239
; RV64IMB: # %bb.0:
240-
; RV64IMB-NEXT: addiw a0, a0, 1000
240+
; RV64IMB-NEXT: addi a0, a0, 1000
241241
; RV64IMB-NEXT: sh3add a1, a0, a0
242242
; RV64IMB-NEXT: sh3add a0, a1, a0
243243
; RV64IMB-NEXT: sext.w a0, a0
@@ -349,7 +349,7 @@ define i32 @add_mul_combine_reject_e1(i32 %x) {
349349
;
350350
; RV64IMB-LABEL: add_mul_combine_reject_e1:
351351
; RV64IMB: # %bb.0:
352-
; RV64IMB-NEXT: addiw a0, a0, 1971
352+
; RV64IMB-NEXT: addi a0, a0, 1971
353353
; RV64IMB-NEXT: li a1, 29
354354
; RV64IMB-NEXT: mulw a0, a0, a1
355355
; RV64IMB-NEXT: ret
@@ -368,7 +368,7 @@ define signext i32 @add_mul_combine_reject_e2(i32 signext %x) {
368368
;
369369
; RV64IMB-LABEL: add_mul_combine_reject_e2:
370370
; RV64IMB: # %bb.0:
371-
; RV64IMB-NEXT: addiw a0, a0, 1971
371+
; RV64IMB-NEXT: addi a0, a0, 1971
372372
; RV64IMB-NEXT: li a1, 29
373373
; RV64IMB-NEXT: mulw a0, a0, a1
374374
; RV64IMB-NEXT: ret
@@ -414,7 +414,7 @@ define i32 @add_mul_combine_reject_f1(i32 %x) {
414414
;
415415
; RV64IMB-LABEL: add_mul_combine_reject_f1:
416416
; RV64IMB: # %bb.0:
417-
; RV64IMB-NEXT: addiw a0, a0, 1972
417+
; RV64IMB-NEXT: addi a0, a0, 1972
418418
; RV64IMB-NEXT: li a1, 29
419419
; RV64IMB-NEXT: mul a0, a0, a1
420420
; RV64IMB-NEXT: addiw a0, a0, 11
@@ -435,7 +435,7 @@ define signext i32 @add_mul_combine_reject_f2(i32 signext %x) {
435435
;
436436
; RV64IMB-LABEL: add_mul_combine_reject_f2:
437437
; RV64IMB: # %bb.0:
438-
; RV64IMB-NEXT: addiw a0, a0, 1972
438+
; RV64IMB-NEXT: addi a0, a0, 1972
439439
; RV64IMB-NEXT: li a1, 29
440440
; RV64IMB-NEXT: mul a0, a0, a1
441441
; RV64IMB-NEXT: addiw a0, a0, 11
@@ -483,7 +483,7 @@ define i32 @add_mul_combine_reject_g1(i32 %x) {
483483
;
484484
; RV64IMB-LABEL: add_mul_combine_reject_g1:
485485
; RV64IMB: # %bb.0:
486-
; RV64IMB-NEXT: addiw a0, a0, 100
486+
; RV64IMB-NEXT: addi a0, a0, 100
487487
; RV64IMB-NEXT: sh3add a1, a0, a0
488488
; RV64IMB-NEXT: sh3add a0, a1, a0
489489
; RV64IMB-NEXT: addiw a0, a0, 10
@@ -504,7 +504,7 @@ define signext i32 @add_mul_combine_reject_g2(i32 signext %x) {
504504
;
505505
; RV64IMB-LABEL: add_mul_combine_reject_g2:
506506
; RV64IMB: # %bb.0:
507-
; RV64IMB-NEXT: addiw a0, a0, 100
507+
; RV64IMB-NEXT: addi a0, a0, 100
508508
; RV64IMB-NEXT: sh3add a1, a0, a0
509509
; RV64IMB-NEXT: sh3add a0, a1, a0
510510
; RV64IMB-NEXT: addiw a0, a0, 10
@@ -581,9 +581,9 @@ define i32 @mul3000_add8990_a(i32 %x) {
581581
;
582582
; RV64IMB-LABEL: mul3000_add8990_a:
583583
; RV64IMB: # %bb.0:
584-
; RV64IMB-NEXT: addiw a0, a0, 3
584+
; RV64IMB-NEXT: addi a0, a0, 3
585585
; RV64IMB-NEXT: lui a1, 1
586-
; RV64IMB-NEXT: addiw a1, a1, -1096
586+
; RV64IMB-NEXT: addi a1, a1, -1096
587587
; RV64IMB-NEXT: mul a0, a0, a1
588588
; RV64IMB-NEXT: addiw a0, a0, -10
589589
; RV64IMB-NEXT: ret
@@ -604,9 +604,9 @@ define signext i32 @mul3000_add8990_b(i32 signext %x) {
604604
;
605605
; RV64IMB-LABEL: mul3000_add8990_b:
606606
; RV64IMB: # %bb.0:
607-
; RV64IMB-NEXT: addiw a0, a0, 3
607+
; RV64IMB-NEXT: addi a0, a0, 3
608608
; RV64IMB-NEXT: lui a1, 1
609-
; RV64IMB-NEXT: addiw a1, a1, -1096
609+
; RV64IMB-NEXT: addi a1, a1, -1096
610610
; RV64IMB-NEXT: mul a0, a0, a1
611611
; RV64IMB-NEXT: addiw a0, a0, -10
612612
; RV64IMB-NEXT: ret
@@ -656,9 +656,9 @@ define i32 @mul3000_sub8990_a(i32 %x) {
656656
;
657657
; RV64IMB-LABEL: mul3000_sub8990_a:
658658
; RV64IMB: # %bb.0:
659-
; RV64IMB-NEXT: addiw a0, a0, -3
659+
; RV64IMB-NEXT: addi a0, a0, -3
660660
; RV64IMB-NEXT: lui a1, 1
661-
; RV64IMB-NEXT: addiw a1, a1, -1096
661+
; RV64IMB-NEXT: addi a1, a1, -1096
662662
; RV64IMB-NEXT: mul a0, a0, a1
663663
; RV64IMB-NEXT: addiw a0, a0, 10
664664
; RV64IMB-NEXT: ret
@@ -679,9 +679,9 @@ define signext i32 @mul3000_sub8990_b(i32 signext %x) {
679679
;
680680
; RV64IMB-LABEL: mul3000_sub8990_b:
681681
; RV64IMB: # %bb.0:
682-
; RV64IMB-NEXT: addiw a0, a0, -3
682+
; RV64IMB-NEXT: addi a0, a0, -3
683683
; RV64IMB-NEXT: lui a1, 1
684-
; RV64IMB-NEXT: addiw a1, a1, -1096
684+
; RV64IMB-NEXT: addi a1, a1, -1096
685685
; RV64IMB-NEXT: mul a0, a0, a1
686686
; RV64IMB-NEXT: addiw a0, a0, 10
687687
; RV64IMB-NEXT: ret
@@ -732,9 +732,9 @@ define i32 @mulneg3000_add8990_a(i32 %x) {
732732
;
733733
; RV64IMB-LABEL: mulneg3000_add8990_a:
734734
; RV64IMB: # %bb.0:
735-
; RV64IMB-NEXT: addiw a0, a0, -3
735+
; RV64IMB-NEXT: addi a0, a0, -3
736736
; RV64IMB-NEXT: lui a1, 1048575
737-
; RV64IMB-NEXT: addiw a1, a1, 1096
737+
; RV64IMB-NEXT: addi a1, a1, 1096
738738
; RV64IMB-NEXT: mul a0, a0, a1
739739
; RV64IMB-NEXT: addiw a0, a0, -10
740740
; RV64IMB-NEXT: ret
@@ -755,9 +755,9 @@ define signext i32 @mulneg3000_add8990_b(i32 signext %x) {
755755
;
756756
; RV64IMB-LABEL: mulneg3000_add8990_b:
757757
; RV64IMB: # %bb.0:
758-
; RV64IMB-NEXT: addiw a0, a0, -3
758+
; RV64IMB-NEXT: addi a0, a0, -3
759759
; RV64IMB-NEXT: lui a1, 1048575
760-
; RV64IMB-NEXT: addiw a1, a1, 1096
760+
; RV64IMB-NEXT: addi a1, a1, 1096
761761
; RV64IMB-NEXT: mul a0, a0, a1
762762
; RV64IMB-NEXT: addiw a0, a0, -10
763763
; RV64IMB-NEXT: ret
@@ -808,9 +808,9 @@ define i32 @mulneg3000_sub8990_a(i32 %x) {
808808
;
809809
; RV64IMB-LABEL: mulneg3000_sub8990_a:
810810
; RV64IMB: # %bb.0:
811-
; RV64IMB-NEXT: addiw a0, a0, 3
811+
; RV64IMB-NEXT: addi a0, a0, 3
812812
; RV64IMB-NEXT: lui a1, 1048575
813-
; RV64IMB-NEXT: addiw a1, a1, 1096
813+
; RV64IMB-NEXT: addi a1, a1, 1096
814814
; RV64IMB-NEXT: mul a0, a0, a1
815815
; RV64IMB-NEXT: addiw a0, a0, 10
816816
; RV64IMB-NEXT: ret
@@ -831,9 +831,9 @@ define signext i32 @mulneg3000_sub8990_b(i32 signext %x) {
831831
;
832832
; RV64IMB-LABEL: mulneg3000_sub8990_b:
833833
; RV64IMB: # %bb.0:
834-
; RV64IMB-NEXT: addiw a0, a0, 3
834+
; RV64IMB-NEXT: addi a0, a0, 3
835835
; RV64IMB-NEXT: lui a1, 1048575
836-
; RV64IMB-NEXT: addiw a1, a1, 1096
836+
; RV64IMB-NEXT: addi a1, a1, 1096
837837
; RV64IMB-NEXT: mul a0, a0, a1
838838
; RV64IMB-NEXT: addiw a0, a0, 10
839839
; RV64IMB-NEXT: ret

‎llvm/test/CodeGen/RISCV/and.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -195,7 +195,7 @@ define i64 @and64_0x7fffffff00000000(i64 %x) {
195195
; RV64I-LABEL: and64_0x7fffffff00000000:
196196
; RV64I: # %bb.0:
197197
; RV64I-NEXT: lui a1, 524288
198-
; RV64I-NEXT: addiw a1, a1, -1
198+
; RV64I-NEXT: addi a1, a1, -1
199199
; RV64I-NEXT: slli a1, a1, 32
200200
; RV64I-NEXT: and a0, a0, a1
201201
; RV64I-NEXT: ret

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