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chuongg3chuongg3
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[AArch64][NFC] Pre-commit test for Push ADD/SUB through {S|Z}EXT (#90964)
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‎llvm/test/CodeGen/AArch64/GlobalISel/combine-add.mir

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@@ -207,3 +207,122 @@ body: |
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%3:_(<4 x s32>) = G_FADD %0, %2(<4 x s32>)
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$q0 = COPY %3(<4 x s32>)
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...
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---
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name: saddl_v8i8_v8i32
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $d0, $d1
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; CHECK-LABEL: name: saddl_v8i8_v8i32
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; CHECK: liveins: $d0, $d1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
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; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(<8 x s32>) = G_SEXT [[COPY]](<8 x s8>)
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; CHECK-NEXT: [[SEXT1:%[0-9]+]]:_(<8 x s32>) = G_SEXT [[COPY1]](<8 x s8>)
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; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<8 x s32>) = G_ADD [[SEXT]], [[SEXT1]]
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; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[ADD]](<8 x s32>)
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; CHECK-NEXT: $q0 = COPY [[UV]](<4 x s32>)
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; CHECK-NEXT: $q1 = COPY [[UV1]](<4 x s32>)
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; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
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%0:_(<8 x s8>) = COPY $d0
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%1:_(<8 x s8>) = COPY $d1
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%2:_(<8 x s32>) = G_SEXT %0(<8 x s8>)
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%3:_(<8 x s32>) = G_SEXT %1(<8 x s8>)
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%4:_(<8 x s32>) = G_ADD %2, %3
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%5:_(<4 x s32>), %6:_(<4 x s32>) = G_UNMERGE_VALUES %4(<8 x s32>)
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$q0 = COPY %5(<4 x s32>)
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$q1 = COPY %6(<4 x s32>)
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RET_ReallyLR implicit $q0, implicit $q1
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...
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---
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name: uaddl_v8i8_v8i32
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $d0, $d1
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; CHECK-LABEL: name: uaddl_v8i8_v8i32
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; CHECK: liveins: $d0, $d1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
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; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(<8 x s32>) = G_ZEXT [[COPY]](<8 x s8>)
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; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(<8 x s32>) = G_ZEXT [[COPY1]](<8 x s8>)
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; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<8 x s32>) = G_ADD [[ZEXT]], [[ZEXT1]]
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; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[ADD]](<8 x s32>)
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; CHECK-NEXT: $q0 = COPY [[UV]](<4 x s32>)
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; CHECK-NEXT: $q1 = COPY [[UV1]](<4 x s32>)
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; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
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%0:_(<8 x s8>) = COPY $d0
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%1:_(<8 x s8>) = COPY $d1
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%2:_(<8 x s32>) = G_ZEXT %0(<8 x s8>)
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%3:_(<8 x s32>) = G_ZEXT %1(<8 x s8>)
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%4:_(<8 x s32>) = G_ADD %2, %3
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%5:_(<4 x s32>), %6:_(<4 x s32>) = G_UNMERGE_VALUES %4(<8 x s32>)
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$q0 = COPY %5(<4 x s32>)
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$q1 = COPY %6(<4 x s32>)
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RET_ReallyLR implicit $q0, implicit $q1
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...
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---
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name: ssubl_v8i8_v8i32
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $d0, $d1
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; CHECK-LABEL: name: ssubl_v8i8_v8i32
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; CHECK: liveins: $d0, $d1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
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; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(<8 x s32>) = G_SEXT [[COPY]](<8 x s8>)
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; CHECK-NEXT: [[SEXT1:%[0-9]+]]:_(<8 x s32>) = G_SEXT [[COPY1]](<8 x s8>)
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; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<8 x s32>) = G_SUB [[SEXT]], [[SEXT1]]
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; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[SUB]](<8 x s32>)
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; CHECK-NEXT: $q0 = COPY [[UV]](<4 x s32>)
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; CHECK-NEXT: $q1 = COPY [[UV1]](<4 x s32>)
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; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
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%0:_(<8 x s8>) = COPY $d0
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%1:_(<8 x s8>) = COPY $d1
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%2:_(<8 x s32>) = G_SEXT %0(<8 x s8>)
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%3:_(<8 x s32>) = G_SEXT %1(<8 x s8>)
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%4:_(<8 x s32>) = G_SUB %2, %3
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%5:_(<4 x s32>), %6:_(<4 x s32>) = G_UNMERGE_VALUES %4(<8 x s32>)
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$q0 = COPY %5(<4 x s32>)
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$q1 = COPY %6(<4 x s32>)
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RET_ReallyLR implicit $q0, implicit $q1
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...
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---
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name: usubl_v8i8_v8i32
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tracksRegLiveness: true
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body: |
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bb.1:
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liveins: $d0, $d1
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; CHECK-LABEL: name: usubl_v8i8_v8i32
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; CHECK: liveins: $d0, $d1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
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; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(<8 x s32>) = G_ZEXT [[COPY]](<8 x s8>)
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; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(<8 x s32>) = G_ZEXT [[COPY1]](<8 x s8>)
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; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<8 x s32>) = G_SUB [[ZEXT]], [[ZEXT1]]
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; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[SUB]](<8 x s32>)
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; CHECK-NEXT: $q0 = COPY [[UV]](<4 x s32>)
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; CHECK-NEXT: $q1 = COPY [[UV1]](<4 x s32>)
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; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
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%0:_(<8 x s8>) = COPY $d0
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%1:_(<8 x s8>) = COPY $d1
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%2:_(<8 x s32>) = G_ZEXT %0(<8 x s8>)
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%3:_(<8 x s32>) = G_ZEXT %1(<8 x s8>)
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%4:_(<8 x s32>) = G_SUB %2, %3
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%5:_(<4 x s32>), %6:_(<4 x s32>) = G_UNMERGE_VALUES %4(<8 x s32>)
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$q0 = COPY %5(<4 x s32>)
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$q1 = COPY %6(<4 x s32>)
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RET_ReallyLR implicit $q0, implicit $q1
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...

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