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[AArch64][SME2] Add multi-vector FP convert from Float to interleave Half/BFloat intrinsic
Add the following intrinsic: FCVTN BFCVTN NOTE: These intrinsics are still in development and are subject to future changes. Reviewed By: david-arm Differential Revision: https://reviews.llvm.org/D142025
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‎llvm/include/llvm/IR/IntrinsicsAArch64.td

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@@ -2752,6 +2752,17 @@ let TargetPrefix = "aarch64" in {
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LLVMMatchType<0>, llvm_i32_ty],
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[ImmArg<ArgIndex<6>>]>;
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class SME2_CVT_VG2_SINGLE_Intrinsic
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: DefaultAttrsIntrinsic<[LLVMSubdivide2VectorType<0>],
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[llvm_anyvector_ty, LLVMMatchType<0>],
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[IntrNoMem]>;
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class SME2_CVT_VG2_SINGLE_BF16_Intrinsic
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: DefaultAttrsIntrinsic<[llvm_nxv8bf16_ty],
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[llvm_nxv4f32_ty, llvm_nxv4f32_ty],
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[IntrNoMem]>;
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//
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// Multi-vector fused multiply-add/subtract
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//
@@ -2804,4 +2815,10 @@ let TargetPrefix = "aarch64" in {
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def int_aarch64_sme_suvdot_lane_za32_vg1x4 : SME2_Matrix_ArrayVector_VG4_Multi_Index_Intrinsic;
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def int_aarch64_sme_usvdot_lane_za32_vg1x4 : SME2_Matrix_ArrayVector_VG4_Multi_Index_Intrinsic;
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//
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// Multi-vector floating-point CVT from single-precision to interleaved half-precision/BFloat16
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//
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def int_aarch64_sve_fcvtn_x2 : SME2_CVT_VG2_SINGLE_Intrinsic;
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def int_aarch64_sve_bfcvtn_x2 : SME2_CVT_VG2_SINGLE_BF16_Intrinsic;
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}

‎llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td

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@@ -363,14 +363,14 @@ defm UMLSL_VG4_M4ZZ : sme2_int_mla_long_array_vg4_single<"umlsl", 0b11, int_aar
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defm UMLSL_VG2_M2Z2Z : sme2_int_mla_long_array_vg2_multi<"umlsl", 0b11, int_aarch64_sme_umlsl_vg2x2>;
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defm UMLSL_VG4_M4Z4Z : sme2_int_mla_long_array_vg4_multi<"umlsl", 0b11, int_aarch64_sme_umlsl_vg2x4>;
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defm FCVT_Z2Z_StoH : sme2_cvt_vg2_single<"fcvt", 0b0000>;
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defm FCVTN_Z2Z_StoH : sme2_cvt_vg2_single<"fcvtn", 0b0001>;
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defm BFCVT_Z2Z_StoH : sme2_cvt_vg2_single<"bfcvt", 0b1000>;
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defm BFCVTN_Z2Z_StoH : sme2_cvt_vg2_single<"bfcvtn", 0b1001>;
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defm SQCVT_Z2Z_StoH : sme2_cvt_vg2_single<"sqcvt", 0b0110>;
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defm UQCVT_Z2Z_StoH : sme2_cvt_vg2_single<"uqcvt", 0b0111>;
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defm SQCVTU_Z2Z_StoH : sme2_cvt_vg2_single<"sqcvtu", 0b1110>;
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defm FCVT_Z2Z_StoH : sme2_cvt_vg2_single<"fcvt", 0b0000, nxv8f16, nxv4f32, null_frag>;
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defm FCVTN_Z2Z_StoH : sme2_cvt_vg2_single<"fcvtn", 0b0001, nxv8f16, nxv4f32, int_aarch64_sve_fcvtn_x2>;
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defm BFCVT_Z2Z_StoH : sme2_cvt_vg2_single<"bfcvt", 0b1000, nxv8bf16, nxv4f32, null_frag>;
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defm BFCVTN_Z2Z_StoH : sme2_cvt_vg2_single<"bfcvtn", 0b1001, nxv8bf16, nxv4f32, int_aarch64_sve_bfcvtn_x2>;
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defm SQCVT_Z2Z_StoH : sme2_cvt_vg2_single<"sqcvt", 0b0110, nxv8i16, nxv4i32, null_frag>;
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defm UQCVT_Z2Z_StoH : sme2_cvt_vg2_single<"uqcvt", 0b0111, nxv8i16, nxv4i32, null_frag>;
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defm SQCVTU_Z2Z_StoH : sme2_cvt_vg2_single<"sqcvtu", 0b1110, nxv8i16, nxv4i32, null_frag>;
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defm SQCVT_Z4Z : sme2_int_cvt_vg4_single<"sqcvt", 0b000>;
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defm UQCVT_Z4Z : sme2_int_cvt_vg4_single<"uqcvt", 0b001>;
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defm SQCVTU_Z4Z : sme2_int_cvt_vg4_single<"sqcvtu", 0b100>;

‎llvm/lib/Target/AArch64/SMEInstrFormats.td

Lines changed: 7 additions & 1 deletion
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@@ -133,6 +133,10 @@ class SME2_ZA_TwoOp_VG4_Multi_Index_Pat<string name, SDPatternOperator intrinsic
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(REG_SEQUENCE ZPR4Mul4, vt:$Zn1, zsub0, vt:$Zn2, zsub1, vt:$Zn3, zsub2, vt:$Zn4, zsub3),
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zpr_ty:$Zm, imm_ty:$i)>;
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class SME2_Cvt_VG2_Pat<string name, SDPatternOperator intrinsic, ValueType out_vt, ValueType in_vt>
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: Pat<(out_vt (intrinsic in_vt:$Zn1, in_vt:$Zn2)),
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(!cast<Instruction>(name) (REG_SEQUENCE ZPR2Mul2, in_vt:$Zn1, zsub0, in_vt:$Zn2, zsub1))>;
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//===----------------------------------------------------------------------===//
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// SME Outer Products
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//===----------------------------------------------------------------------===//
@@ -2063,8 +2067,10 @@ class sme2_cvt_vg2_single<string mnemonic, bits<4> op>
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// SME2 multi-vec FP down convert two registers
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// SME2 multi-vec int down convert two registers
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multiclass sme2_cvt_vg2_single<string mnemonic, bits<4> op> {
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multiclass sme2_cvt_vg2_single<string mnemonic, bits<4> op, ValueType out_vt,
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ValueType in_vt, SDPatternOperator intrinsic> {
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def NAME : sme2_cvt_vg2_single<mnemonic, op>;
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def : SME2_Cvt_VG2_Pat<NAME, intrinsic, out_vt, in_vt>;
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}
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class sme2_cvt_unpk_vector_vg2<bits<2>sz, bits<3> op, bit u, RegisterOperand first_ty,

‎llvm/test/CodeGen/AArch64/sme2-intrinsics-cvtn.ll

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@@ -0,0 +1,34 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2,+bf16 -verify-machineinstrs < %s | FileCheck %s
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;
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; FCVTN
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;
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define <vscale x 8 x half> @multi_vector_cvtn_x2_f16(<vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2) {
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; CHECK-LABEL: multi_vector_cvtn_x2_f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1
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; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1
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; CHECK-NEXT: fcvtn z0.h, { z0.s, z1.s }
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x half> @llvm.aarch64.sve.fcvtn.x2.nxv4f32(<vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2)
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ret <vscale x 8 x half> %res
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}
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;
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; BFCVTN
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;
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define <vscale x 8 x bfloat> @multi_vector_bfcvtn_x2(<vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2) {
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; CHECK-LABEL: multi_vector_bfcvtn_x2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1
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; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1
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; CHECK-NEXT: bfcvtn z0.h, { z0.s, z1.s }
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.bfcvtn.x2(<vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2)
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ret <vscale x 8 x bfloat> %res
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}
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declare <vscale x 8 x half> @llvm.aarch64.sve.fcvtn.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>)
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declare <vscale x 8 x bfloat> @llvm.aarch64.sve.bfcvtn.x2(<vscale x 4 x float>, <vscale x 4 x float>)

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