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[RISCV][MC] Emit x8 as fp instead of s0 (#135500)
When emphasizing `X8`'s functionality related to Frame Pointer, this option can be passed.
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‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp

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@@ -34,6 +34,10 @@ static cl::opt<bool>
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cl::desc("Disable the emission of assembler pseudo instructions"),
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cl::init(false), cl::Hidden);
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static cl::opt<bool> EmitX8AsFP("riscv-emit-x8-as-fp",
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cl::desc("Emit x8 as fp instead of s0"),
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cl::init(false), cl::Hidden);
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// Print architectural register names rather than the ABI names (such as x2
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// instead of sp).
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// TODO: Make RISCVInstPrinter::getRegisterName non-static so that this can a
@@ -54,6 +58,11 @@ bool RISCVInstPrinter::applyTargetSpecificCLOption(StringRef Opt) {
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ArchRegNames = true;
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return true;
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}
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if (Opt == "emit-x8-as-fp") {
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if (!ArchRegNames)
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EmitX8AsFP = true;
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return true;
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}
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return false;
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}
@@ -311,6 +320,13 @@ void RISCVInstPrinter::printVMaskReg(const MCInst *MI, unsigned OpNo,
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}
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const char *RISCVInstPrinter::getRegisterName(MCRegister Reg) {
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// When PrintAliases is enabled, and EmitX8AsFP is enabled, x8 will be printed
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// as fp instead of s0. Note that these similar registers are not replaced:
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// - X8_H: used for f16 register in zhinx
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// - X8_W: used for f32 register in zfinx
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// - X8_X9: used for GPR Pair
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if (!ArchRegNames && EmitX8AsFP && Reg == RISCV::X8)
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return "fp";
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return getRegisterName(Reg, ArchRegNames ? RISCV::NoRegAltName
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: RISCV::ABIRegAltName);
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}

‎llvm/test/CodeGen/RISCV/emit-x8-as-fp.ll

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@@ -0,0 +1,121 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I-DEFAULT %s
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I-DEFAULT %s
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; RUN: llc -mtriple=riscv32 -M emit-x8-as-fp -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I-EMIT-FP %s
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; RUN: llc -mtriple=riscv64 -M emit-x8-as-fp -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I-EMIT-FP %s
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; RUN: llc -mtriple=riscv32 -M numeric -M emit-x8-as-fp -verify-machineinstrs \
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; RUN: < %s | FileCheck -check-prefix=RV32I-NUMERIC %s
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; RUN: llc -mtriple=riscv64 -M numeric -M emit-x8-as-fp -verify-machineinstrs \
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; RUN: < %s | FileCheck -check-prefix=RV64I-NUMERIC %s
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define signext i32 @add(i32 %0, i32 %1) #0 {
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; RV32I-DEFAULT-LABEL: add:
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; RV32I-DEFAULT: # %bb.0:
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; RV32I-DEFAULT-NEXT: addi sp, sp, -16
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; RV32I-DEFAULT-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-DEFAULT-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
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; RV32I-DEFAULT-NEXT: addi s0, sp, 16
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; RV32I-DEFAULT-NEXT: sw a0, -12(s0)
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; RV32I-DEFAULT-NEXT: sw a1, -16(s0)
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; RV32I-DEFAULT-NEXT: lw a0, -12(s0)
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; RV32I-DEFAULT-NEXT: lw a1, -16(s0)
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; RV32I-DEFAULT-NEXT: add a0, a0, a1
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; RV32I-DEFAULT-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-DEFAULT-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
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; RV32I-DEFAULT-NEXT: addi sp, sp, 16
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; RV32I-DEFAULT-NEXT: ret
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;
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; RV64I-DEFAULT-LABEL: add:
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; RV64I-DEFAULT: # %bb.0:
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; RV64I-DEFAULT-NEXT: addi sp, sp, -32
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; RV64I-DEFAULT-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
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; RV64I-DEFAULT-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
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; RV64I-DEFAULT-NEXT: addi s0, sp, 32
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; RV64I-DEFAULT-NEXT: sw a0, -20(s0)
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; RV64I-DEFAULT-NEXT: sw a1, -24(s0)
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; RV64I-DEFAULT-NEXT: lw a0, -20(s0)
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; RV64I-DEFAULT-NEXT: lw a1, -24(s0)
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; RV64I-DEFAULT-NEXT: addw a0, a0, a1
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; RV64I-DEFAULT-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
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; RV64I-DEFAULT-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
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; RV64I-DEFAULT-NEXT: addi sp, sp, 32
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; RV64I-DEFAULT-NEXT: ret
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;
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; RV32I-EMIT-FP-LABEL: add:
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; RV32I-EMIT-FP: # %bb.0:
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; RV32I-EMIT-FP-NEXT: addi sp, sp, -16
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; RV32I-EMIT-FP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32I-EMIT-FP-NEXT: sw fp, 8(sp) # 4-byte Folded Spill
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; RV32I-EMIT-FP-NEXT: addi fp, sp, 16
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; RV32I-EMIT-FP-NEXT: sw a0, -12(fp)
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; RV32I-EMIT-FP-NEXT: sw a1, -16(fp)
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; RV32I-EMIT-FP-NEXT: lw a0, -12(fp)
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; RV32I-EMIT-FP-NEXT: lw a1, -16(fp)
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; RV32I-EMIT-FP-NEXT: add a0, a0, a1
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; RV32I-EMIT-FP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
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; RV32I-EMIT-FP-NEXT: lw fp, 8(sp) # 4-byte Folded Reload
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; RV32I-EMIT-FP-NEXT: addi sp, sp, 16
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; RV32I-EMIT-FP-NEXT: ret
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;
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; RV64I-EMIT-FP-LABEL: add:
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; RV64I-EMIT-FP: # %bb.0:
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; RV64I-EMIT-FP-NEXT: addi sp, sp, -32
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; RV64I-EMIT-FP-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
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; RV64I-EMIT-FP-NEXT: sd fp, 16(sp) # 8-byte Folded Spill
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; RV64I-EMIT-FP-NEXT: addi fp, sp, 32
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; RV64I-EMIT-FP-NEXT: sw a0, -20(fp)
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; RV64I-EMIT-FP-NEXT: sw a1, -24(fp)
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; RV64I-EMIT-FP-NEXT: lw a0, -20(fp)
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; RV64I-EMIT-FP-NEXT: lw a1, -24(fp)
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; RV64I-EMIT-FP-NEXT: addw a0, a0, a1
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; RV64I-EMIT-FP-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
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; RV64I-EMIT-FP-NEXT: ld fp, 16(sp) # 8-byte Folded Reload
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; RV64I-EMIT-FP-NEXT: addi sp, sp, 32
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; RV64I-EMIT-FP-NEXT: ret
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;
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; RV32I-NUMERIC-LABEL: add:
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; RV32I-NUMERIC: # %bb.0:
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; RV32I-NUMERIC-NEXT: addi x2, x2, -16
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; RV32I-NUMERIC-NEXT: sw x1, 12(x2) # 4-byte Folded Spill
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; RV32I-NUMERIC-NEXT: sw x8, 8(x2) # 4-byte Folded Spill
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; RV32I-NUMERIC-NEXT: addi x8, x2, 16
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; RV32I-NUMERIC-NEXT: sw x10, -12(x8)
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; RV32I-NUMERIC-NEXT: sw x11, -16(x8)
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; RV32I-NUMERIC-NEXT: lw x10, -12(x8)
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; RV32I-NUMERIC-NEXT: lw x11, -16(x8)
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; RV32I-NUMERIC-NEXT: add x10, x10, x11
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; RV32I-NUMERIC-NEXT: lw x1, 12(x2) # 4-byte Folded Reload
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; RV32I-NUMERIC-NEXT: lw x8, 8(x2) # 4-byte Folded Reload
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; RV32I-NUMERIC-NEXT: addi x2, x2, 16
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; RV32I-NUMERIC-NEXT: ret
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;
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; RV64I-NUMERIC-LABEL: add:
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; RV64I-NUMERIC: # %bb.0:
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; RV64I-NUMERIC-NEXT: addi x2, x2, -32
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; RV64I-NUMERIC-NEXT: sd x1, 24(x2) # 8-byte Folded Spill
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; RV64I-NUMERIC-NEXT: sd x8, 16(x2) # 8-byte Folded Spill
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; RV64I-NUMERIC-NEXT: addi x8, x2, 32
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; RV64I-NUMERIC-NEXT: sw x10, -20(x8)
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; RV64I-NUMERIC-NEXT: sw x11, -24(x8)
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; RV64I-NUMERIC-NEXT: lw x10, -20(x8)
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; RV64I-NUMERIC-NEXT: lw x11, -24(x8)
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; RV64I-NUMERIC-NEXT: addw x10, x10, x11
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; RV64I-NUMERIC-NEXT: ld x1, 24(x2) # 8-byte Folded Reload
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; RV64I-NUMERIC-NEXT: ld x8, 16(x2) # 8-byte Folded Reload
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; RV64I-NUMERIC-NEXT: addi x2, x2, 32
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; RV64I-NUMERIC-NEXT: ret
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%3 = alloca i32, align 4
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%4 = alloca i32, align 4
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store i32 %0, ptr %3, align 4
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store i32 %1, ptr %4, align 4
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%5 = load i32, ptr %3, align 4
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%6 = load i32, ptr %4, align 4
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%7 = add nsw i32 %5, %6
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ret i32 %7
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}
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attributes #0 = { noinline nounwind optnone "frame-pointer"="all" }

‎llvm/test/MC/Disassembler/RISCV/emit-x8-as-fp.txt

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# RUN: llvm-mc --disassemble -triple=riscv32 --show-encoding < %s \
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# RUN: | FileCheck --check-prefixes=DEFAULT %s
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# RUN: llvm-mc --disassemble -triple=riscv64 --show-encoding < %s \
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# RUN: | FileCheck --check-prefixes=DEFAULT %s
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# RUN: llvm-mc --disassemble -triple=riscv32 -M emit-x8-as-fp \
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# RUN: --show-encoding < %s | FileCheck --check-prefixes=EMIT-FP %s
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# RUN: llvm-mc --disassemble -triple=riscv64 -M emit-x8-as-fp \
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# RUN: --show-encoding < %s | FileCheck --check-prefixes=EMIT-FP %s
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# RUN: llvm-mc --disassemble -triple=riscv32 -M numeric -M emit-x8-as-fp \
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# RUN: --show-encoding < %s | FileCheck --check-prefixes=NUMERIC %s
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# RUN: llvm-mc --disassemble -triple=riscv64 -M numeric -M emit-x8-as-fp \
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# RUN: --show-encoding < %s | FileCheck --check-prefixes=NUMERIC %s
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# DEFAULT: sw a0, -12(s0) # encoding: [0x23,0x2a,0xa4,0xfe]
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# EMIT-FP: sw a0, -12(fp) # encoding: [0x23,0x2a,0xa4,0xfe]
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# NUMERIC: sw x10, -12(x8) # encoding: [0x23,0x2a,0xa4,0xfe]
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0x23 0x2a 0xa4 0xfe
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# DEFAULT: lw a0, -12(s0) # encoding: [0x03,0x25,0x44,0xff]
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# EMIT-FP: lw a0, -12(fp) # encoding: [0x03,0x25,0x44,0xff]
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# NUMERIC: lw x10, -12(x8) # encoding: [0x03,0x25,0x44,0xff]
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0x03 0x25 0x44 0xff

‎llvm/test/MC/RISCV/emit-x8-as-fp.s

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# RUN: llvm-mc --triple=riscv32 --show-encoding < %s 2>&1 \
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# RUN: | FileCheck --check-prefix=DEFAULT %s
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# RUN: llvm-mc --triple=riscv64 --show-encoding < %s 2>&1 \
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# RUN: | FileCheck --check-prefix=DEFAULT %s
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# RUN: llvm-mc --triple=riscv32 -M emit-x8-as-fp --show-encoding < %s 2>&1 \
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# RUN: | FileCheck --check-prefix=EMIT-FP %s
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# RUN: llvm-mc --triple=riscv64 -M emit-x8-as-fp --show-encoding < %s 2>&1 \
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# RUN: | FileCheck --check-prefix=EMIT-FP %s
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# RUN: llvm-mc --triple=riscv32 -M numeric -M emit-x8-as-fp --show-encoding \
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# RUN: < %s 2>&1 | FileCheck --check-prefix=NUMERIC %s
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# RUN: llvm-mc --triple=riscv64 -M numeric -M emit-x8-as-fp --show-encoding \
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# RUN: < %s 2>&1 | FileCheck --check-prefix=NUMERIC %s
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# DEFAULT: sw a0, -12(s0) # encoding: [0x23,0x2a,0xa4,0xfe]
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# EMIT-FP: sw a0, -12(fp) # encoding: [0x23,0x2a,0xa4,0xfe]
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# NUMERIC: sw x10, -12(x8) # encoding: [0x23,0x2a,0xa4,0xfe]
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sw a0, -12(s0)
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# DEFAULT: lw a0, -12(s0) # encoding: [0x03,0x25,0x44,0xff]
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# EMIT-FP: lw a0, -12(fp) # encoding: [0x03,0x25,0x44,0xff]
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# NUMERIC: lw x10, -12(x8) # encoding: [0x03,0x25,0x44,0xff]
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lw a0, -12(s0)
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# DEFAULT: sw a0, -12(s0) # encoding: [0x23,0x2a,0xa4,0xfe]
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# EMIT-FP: sw a0, -12(fp) # encoding: [0x23,0x2a,0xa4,0xfe]
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# NUMERIC: sw x10, -12(x8) # encoding: [0x23,0x2a,0xa4,0xfe]
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sw a0, -12(fp)
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# DEFAULT: lw a0, -12(s0) # encoding: [0x03,0x25,0x44,0xff]
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# EMIT-FP: lw a0, -12(fp) # encoding: [0x03,0x25,0x44,0xff]
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# NUMERIC: lw x10, -12(x8) # encoding: [0x03,0x25,0x44,0xff]
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lw a0, -12(fp)
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# DEFAULT: sw a0, -12(s0) # encoding: [0x23,0x2a,0xa4,0xfe]
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# EMIT-FP: sw a0, -12(fp) # encoding: [0x23,0x2a,0xa4,0xfe]
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# NUMERIC: sw x10, -12(x8) # encoding: [0x23,0x2a,0xa4,0xfe]
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sw a0, -12(x8)
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# DEFAULT: lw a0, -12(s0) # encoding: [0x03,0x25,0x44,0xff]
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# EMIT-FP: lw a0, -12(fp) # encoding: [0x03,0x25,0x44,0xff]
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# NUMERIC: lw x10, -12(x8) # encoding: [0x03,0x25,0x44,0xff]
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lw a0, -12(x8)

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