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[RISCV] Move vnclip patterns into DAGCombiner. (#93728)
Similar to #93596, this moves the signed vnclip patterns into DAG combine. This will allows us to support more than 1 level of truncate in a future patch.
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3 files changed

+27
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lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 27 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -16183,8 +16183,11 @@ static SDValue combineTruncOfSraSext(SDNode *N, SelectionDAG &DAG) {
1618316183
return DAG.getNode(ISD::SRA, SDLoc(N), N->getValueType(0), N00, SMin);
1618416184
}
1618516185

16186-
// Combine (truncate_vector_vl (umin X, C)) -> (vnclipu_vl X) if C is maximum
16187-
// value for the truncated type.
16186+
// Combine (truncate_vector_vl (umin X, C)) -> (vnclipu_vl X) if C is the
16187+
// maximum value for the truncated type.
16188+
// Combine (truncate_vector_vl (smin (smax X, C2), C1)) -> (vnclip_vl X) if C1
16189+
// is the signed maximum value for the truncated type and C2 is the signed
16190+
// minimum value.
1618816191
static SDValue combineTruncToVnclip(SDNode *N, SelectionDAG &DAG,
1618916192
const RISCVSubtarget &Subtarget) {
1619016193
assert(N->getOpcode() == RISCVISD::TRUNCATE_VECTOR_VL);
@@ -16240,10 +16243,32 @@ static SDValue combineTruncToVnclip(SDNode *N, SelectionDAG &DAG,
1624016243
return UMin;
1624116244
};
1624216245

16246+
auto DetectSSatPattern = [&](SDValue V) {
16247+
unsigned NumDstBits = VT.getScalarSizeInBits();
16248+
unsigned NumSrcBits = V.getScalarValueSizeInBits();
16249+
APInt SignedMax = APInt::getSignedMaxValue(NumDstBits).sext(NumSrcBits);
16250+
APInt SignedMin = APInt::getSignedMinValue(NumDstBits).sext(NumSrcBits);
16251+
16252+
APInt CMin, CMax;
16253+
if (SDValue SMin = MatchMinMax(V, ISD::SMIN, RISCVISD::SMIN_VL, CMin))
16254+
if (SDValue SMax = MatchMinMax(SMin, ISD::SMAX, RISCVISD::SMAX_VL, CMax))
16255+
if (CMin == SignedMax && CMax == SignedMin)
16256+
return SMax;
16257+
16258+
if (SDValue SMax = MatchMinMax(V, ISD::SMAX, RISCVISD::SMAX_VL, CMax))
16259+
if (SDValue SMin = MatchMinMax(SMax, ISD::SMIN, RISCVISD::SMIN_VL, CMin))
16260+
if (CMin == SignedMax && CMax == SignedMin)
16261+
return SMin;
16262+
16263+
return SDValue();
16264+
};
16265+
1624316266
SDValue Val;
1624416267
unsigned ClipOpc;
1624516268
if ((Val = DetectUSatPattern(N->getOperand(0))))
1624616269
ClipOpc = RISCVISD::VNCLIPU_VL;
16270+
else if ((Val = DetectSSatPattern(N->getOperand(0))))
16271+
ClipOpc = RISCVISD::VNCLIP_VL;
1624716272
else
1624816273
return SDValue();
1624916274

‎llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

Lines changed: 0 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -1168,40 +1168,6 @@ defm : VPatAVGADD_VV_VX_RM<avgflooru, 0b10, suffix = "U">;
11681168
defm : VPatAVGADD_VV_VX_RM<avgceils, 0b00>;
11691169
defm : VPatAVGADD_VV_VX_RM<avgceilu, 0b00, suffix = "U">;
11701170

1171-
// 12.5. Vector Narrowing Fixed-Point Clip Instructions
1172-
multiclass VPatTruncSatClipSDNode<VTypeInfo vti, VTypeInfo wti> {
1173-
defvar sew = vti.SEW;
1174-
defvar uminval = !sub(!shl(1, sew), 1);
1175-
defvar sminval = !sub(!shl(1, !sub(sew, 1)), 1);
1176-
defvar smaxval = !sub(0, !shl(1, !sub(sew, 1)));
1177-
1178-
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
1179-
GetVTypePredicates<wti>.Predicates) in {
1180-
def : Pat<(vti.Vector (riscv_trunc_vector_vl
1181-
(wti.Vector (smin
1182-
(wti.Vector (smax (wti.Vector wti.RegClass:$rs1),
1183-
(wti.Vector (riscv_vmv_v_x_vl (wti.Vector undef), smaxval, (XLenVT srcvalue))))),
1184-
(wti.Vector (riscv_vmv_v_x_vl (wti.Vector undef), sminval, (XLenVT srcvalue))))),
1185-
(vti.Mask V0), VLOpFrag)),
1186-
(!cast<Instruction>("PseudoVNCLIP_WI_"#vti.LMul.MX#"_MASK")
1187-
(vti.Vector (IMPLICIT_DEF)), wti.RegClass:$rs1, 0,
1188-
(vti.Mask V0), 0, GPR:$vl, vti.Log2SEW, TA_MA)>;
1189-
1190-
def : Pat<(vti.Vector (riscv_trunc_vector_vl
1191-
(wti.Vector (smax
1192-
(wti.Vector (smin (wti.Vector wti.RegClass:$rs1),
1193-
(wti.Vector (riscv_vmv_v_x_vl (wti.Vector undef), sminval, (XLenVT srcvalue))))),
1194-
(wti.Vector (riscv_vmv_v_x_vl (wti.Vector undef), smaxval, (XLenVT srcvalue))))),
1195-
(vti.Mask V0), VLOpFrag)),
1196-
(!cast<Instruction>("PseudoVNCLIP_WI_"#vti.LMul.MX#"_MASK")
1197-
(vti.Vector (IMPLICIT_DEF)), wti.RegClass:$rs1, 0,
1198-
(vti.Mask V0), 0, GPR:$vl, vti.Log2SEW, TA_MA)>;
1199-
}
1200-
}
1201-
1202-
foreach vtiToWti = AllWidenableIntVectors in
1203-
defm : VPatTruncSatClipSDNode<vtiToWti.Vti, vtiToWti.Wti>;
1204-
12051171
// 15. Vector Mask Instructions
12061172

12071173
// 15.1. Vector Mask-Register Logical Instructions

‎llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

Lines changed: 0 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -2470,46 +2470,6 @@ defm : VPatAVGADDVL_VV_VX_RM<riscv_avgceilu_vl, 0b00, suffix="U">;
24702470
defm : VPatBinaryRM_NVL_WV_WX_WI<riscv_vnclip_vl, "PseudoVNCLIP">;
24712471
defm : VPatBinaryRM_NVL_WV_WX_WI<riscv_vnclipu_vl, "PseudoVNCLIPU">;
24722472

2473-
// 12.5. Vector Narrowing Fixed-Point Clip Instructions
2474-
multiclass VPatTruncSatClipVL<VTypeInfo vti, VTypeInfo wti> {
2475-
defvar sew = vti.SEW;
2476-
defvar uminval = !sub(!shl(1, sew), 1);
2477-
defvar sminval = !sub(!shl(1, !sub(sew, 1)), 1);
2478-
defvar smaxval = !sub(0, !shl(1, !sub(sew, 1)));
2479-
2480-
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
2481-
GetVTypePredicates<wti>.Predicates) in {
2482-
def : Pat<(vti.Vector (riscv_trunc_vector_vl
2483-
(wti.Vector (riscv_smin_vl
2484-
(wti.Vector (riscv_smax_vl
2485-
(wti.Vector wti.RegClass:$rs1),
2486-
(wti.Vector (riscv_vmv_v_x_vl (wti.Vector undef), smaxval, (XLenVT srcvalue))),
2487-
(wti.Vector undef),(wti.Mask V0), VLOpFrag)),
2488-
(wti.Vector (riscv_vmv_v_x_vl (wti.Vector undef), sminval, (XLenVT srcvalue))),
2489-
(wti.Vector undef), (wti.Mask V0), VLOpFrag)),
2490-
(vti.Mask V0), VLOpFrag)),
2491-
(!cast<Instruction>("PseudoVNCLIP_WI_"#vti.LMul.MX#"_MASK")
2492-
(vti.Vector (IMPLICIT_DEF)), wti.RegClass:$rs1, 0,
2493-
(vti.Mask V0), 0, GPR:$vl, vti.Log2SEW, TA_MA)>;
2494-
2495-
def : Pat<(vti.Vector (riscv_trunc_vector_vl
2496-
(wti.Vector (riscv_smax_vl
2497-
(wti.Vector (riscv_smin_vl
2498-
(wti.Vector wti.RegClass:$rs1),
2499-
(wti.Vector (riscv_vmv_v_x_vl (wti.Vector undef), sminval, (XLenVT srcvalue))),
2500-
(wti.Vector undef),(wti.Mask V0), VLOpFrag)),
2501-
(wti.Vector (riscv_vmv_v_x_vl (wti.Vector undef), smaxval, (XLenVT srcvalue))),
2502-
(wti.Vector undef), (wti.Mask V0), VLOpFrag)),
2503-
(vti.Mask V0), VLOpFrag)),
2504-
(!cast<Instruction>("PseudoVNCLIP_WI_"#vti.LMul.MX#"_MASK")
2505-
(vti.Vector (IMPLICIT_DEF)), wti.RegClass:$rs1, 0,
2506-
(vti.Mask V0), 0, GPR:$vl, vti.Log2SEW, TA_MA)>;
2507-
}
2508-
}
2509-
2510-
foreach vtiToWti = AllWidenableIntVectors in
2511-
defm : VPatTruncSatClipVL<vtiToWti.Vti, vtiToWti.Wti>;
2512-
25132473
// 13. Vector Floating-Point Instructions
25142474

25152475
// 13.2. Vector Single-Width Floating-Point Add/Subtract Instructions

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