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[RISCV] Use print-enabled-extensions to check the extensions of Andes n45/nx45/a45/ax45 cpus. NFC. (#140979)
Similarly to what #137725 did for the SiFive P870.
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‎clang/test/Driver/print-enabled-extensions/riscv-andes-a45.c

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// RUN: %clang --target=riscv32 -mcpu=andes-a45 --print-enabled-extensions | FileCheck %s
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// REQUIRES: riscv-registered-target
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// CHECK: Extensions enabled for the given RISC-V target
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// CHECK-EMPTY:
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// CHECK-NEXT: Name Version Description
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// CHECK-NEXT: i 2.1 'I' (Base Integer Instruction Set)
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// CHECK-NEXT: m 2.0 'M' (Integer Multiplication and Division)
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// CHECK-NEXT: a 2.1 'A' (Atomic Instructions)
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// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point)
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// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point)
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// CHECK-NEXT: c 2.0 'C' (Compressed Instructions)
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// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions)
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// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
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// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
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// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication)
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// CHECK-NEXT: zaamo 1.0 'Zaamo' (Atomic Memory Operations)
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// CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional)
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// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores)
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// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions)
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// CHECK-NEXT: zcf 1.0 'Zcf' (Compressed Single-Precision Floating-Point Instructions)
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// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions)
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// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation)
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// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions)
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// CHECK-EMPTY:
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// CHECK-NEXT: Experimental extensions
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// CHECK-EMPTY:
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// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_zba1p0_zbb1p0_zbs1p0

‎clang/test/Driver/print-enabled-extensions/riscv-andes-ax45.c

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// RUN: %clang --target=riscv64 -mcpu=andes-ax45 --print-enabled-extensions | FileCheck %s
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// REQUIRES: riscv-registered-target
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// CHECK: Extensions enabled for the given RISC-V target
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// CHECK-EMPTY:
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// CHECK-NEXT: Name Version Description
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// CHECK-NEXT: i 2.1 'I' (Base Integer Instruction Set)
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// CHECK-NEXT: m 2.0 'M' (Integer Multiplication and Division)
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// CHECK-NEXT: a 2.1 'A' (Atomic Instructions)
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// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point)
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// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point)
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// CHECK-NEXT: c 2.0 'C' (Compressed Instructions)
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// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions)
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// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
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// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
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// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication)
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// CHECK-NEXT: zaamo 1.0 'Zaamo' (Atomic Memory Operations)
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// CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional)
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// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores)
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// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions)
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// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions)
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// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation)
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// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions)
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// CHECK-EMPTY:
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// CHECK-NEXT: Experimental extensions
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// CHECK-EMPTY:
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// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0_zbs1p0

‎clang/test/Driver/print-enabled-extensions/riscv-andes-n45.c

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// RUN: %clang --target=riscv32 -mcpu=andes-n45 --print-enabled-extensions | FileCheck %s
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// REQUIRES: riscv-registered-target
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// CHECK: Extensions enabled for the given RISC-V target
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// CHECK-EMPTY:
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// CHECK-NEXT: Name Version Description
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// CHECK-NEXT: i 2.1 'I' (Base Integer Instruction Set)
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// CHECK-NEXT: m 2.0 'M' (Integer Multiplication and Division)
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// CHECK-NEXT: a 2.1 'A' (Atomic Instructions)
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// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point)
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// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point)
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// CHECK-NEXT: c 2.0 'C' (Compressed Instructions)
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// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions)
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// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
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// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
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// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication)
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// CHECK-NEXT: zaamo 1.0 'Zaamo' (Atomic Memory Operations)
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// CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional)
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// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores)
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// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions)
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// CHECK-NEXT: zcf 1.0 'Zcf' (Compressed Single-Precision Floating-Point Instructions)
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// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions)
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// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation)
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// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions)
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// CHECK-EMPTY:
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// CHECK-NEXT: Experimental extensions
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// CHECK-EMPTY:
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// CHECK-NEXT: ISA String: rv32i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zcf1p0_zba1p0_zbb1p0_zbs1p0

‎clang/test/Driver/print-enabled-extensions/riscv-andes-nx45.c

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// RUN: %clang --target=riscv64 -mcpu=andes-nx45 --print-enabled-extensions | FileCheck %s
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// REQUIRES: riscv-registered-target
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// CHECK: Extensions enabled for the given RISC-V target
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// CHECK-EMPTY:
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// CHECK-NEXT: Name Version Description
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// CHECK-NEXT: i 2.1 'I' (Base Integer Instruction Set)
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// CHECK-NEXT: m 2.0 'M' (Integer Multiplication and Division)
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// CHECK-NEXT: a 2.1 'A' (Atomic Instructions)
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// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point)
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// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point)
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// CHECK-NEXT: c 2.0 'C' (Compressed Instructions)
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// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions)
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// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs)
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// CHECK-NEXT: zifencei 2.0 'Zifencei' (fence.i)
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// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication)
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// CHECK-NEXT: zaamo 1.0 'Zaamo' (Atomic Memory Operations)
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// CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional)
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// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores)
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// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions)
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// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions)
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// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation)
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// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions)
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// CHECK-EMPTY:
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// CHECK-NEXT: Experimental extensions
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// CHECK-EMPTY:
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// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_zicsr2p0_zifencei2p0_zmmul1p0_zaamo1p0_zalrsc1p0_zca1p0_zcd1p0_zba1p0_zbb1p0_zbs1p0

‎clang/test/Driver/riscv-cpus.c

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// MTUNE-ANDES-AX25: "-tune-cpu" "andes-ax25"
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// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=andes-n45 | FileCheck -check-prefix=MCPU-ANDES-N45 %s
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// COM: The list of extensions are tested in `test/Driver/print-enabled-extensions/riscv-andes-n45.c`
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// MCPU-ANDES-N45: "-target-cpu" "andes-n45"
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// MCPU-ANDES-N45-SAME: "-target-feature" "+m"
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// MCPU-ANDES-N45-SAME: "-target-feature" "+a"
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// MCPU-ANDES-N45-SAME: "-target-feature" "+f"
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// MCPU-ANDES-N45-SAME: "-target-feature" "+d"
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// MCPU-ANDES-N45-SAME: "-target-feature" "+c"
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// MCPU-ANDES-N45-SAME: "-target-feature" "+zicsr"
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// MCPU-ANDES-N45-SAME: "-target-feature" "+zifencei"
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// MCPU-ANDES-N45-SAME: "-target-feature" "+zba"
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// MCPU-ANDES-N45-SAME: "-target-feature" "+zbb"
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// MCPU-ANDES-N45-SAME: "-target-feature" "+zbs"
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// MCPU-ANDES-N45-SAME: "-target-abi" "ilp32d"
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// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=andes-n45 | FileCheck -check-prefix=MTUNE-ANDES-N45 %s
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// MTUNE-ANDES-N45: "-tune-cpu" "andes-n45"
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// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=andes-nx45 | FileCheck -check-prefix=MCPU-ANDES-NX45 %s
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// COM: The list of extensions are tested in `test/Driver/print-enabled-extensions/riscv-andes-nx45.c`
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// MCPU-ANDES-NX45: "-target-cpu" "andes-nx45"
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// MCPU-ANDES-NX45-SAME: "-target-feature" "+m"
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// MCPU-ANDES-NX45-SAME: "-target-feature" "+a"
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// MCPU-ANDES-NX45-SAME: "-target-feature" "+f"
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// MCPU-ANDES-NX45-SAME: "-target-feature" "+d"
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// MCPU-ANDES-NX45-SAME: "-target-feature" "+c"
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// MCPU-ANDES-NX45-SAME: "-target-feature" "+zicsr"
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// MCPU-ANDES-NX45-SAME: "-target-feature" "+zifencei"
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// MCPU-ANDES-NX45-SAME: "-target-feature" "+zba"
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// MCPU-ANDES-NX45-SAME: "-target-feature" "+zbb"
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// MCPU-ANDES-NX45-SAME: "-target-feature" "+zbs"
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// MCPU-ANDES-NX45-SAME: "-target-abi" "lp64d"
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// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=andes-nx45 | FileCheck -check-prefix=MTUNE-ANDES-NX45 %s
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// MTUNE-ANDES-NX45: "-tune-cpu" "andes-nx45"
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// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=andes-a45 | FileCheck -check-prefix=MCPU-ANDES-A45 %s
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// COM: The list of extensions are tested in `test/Driver/print-enabled-extensions/riscv-andes-a45.c`
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// MCPU-ANDES-A45: "-target-cpu" "andes-a45"
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// MCPU-ANDES-A45-SAME: "-target-feature" "+m"
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// MCPU-ANDES-A45-SAME: "-target-feature" "+a"
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// MCPU-ANDES-A45-SAME: "-target-feature" "+f"
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// MCPU-ANDES-A45-SAME: "-target-feature" "+d"
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// MCPU-ANDES-A45-SAME: "-target-feature" "+c"
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// MCPU-ANDES-A45-SAME: "-target-feature" "+zicsr"
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// MCPU-ANDES-A45-SAME: "-target-feature" "+zifencei"
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// MCPU-ANDES-A45-SAME: "-target-feature" "+zba"
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// MCPU-ANDES-A45-SAME: "-target-feature" "+zbb"
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// MCPU-ANDES-A45-SAME: "-target-feature" "+zbs"
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// MCPU-ANDES-A45-SAME: "-target-abi" "ilp32d"
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// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=andes-a45 | FileCheck -check-prefix=MTUNE-ANDES-A45 %s
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// MTUNE-ANDES-A45: "-tune-cpu" "andes-a45"
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// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=andes-ax45 | FileCheck -check-prefix=MCPU-ANDES-AX45 %s
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// COM: The list of extensions are tested in `test/Driver/print-enabled-extensions/riscv-andes-ax45.c`
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// MCPU-ANDES-AX45: "-target-cpu" "andes-ax45"
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// MCPU-ANDES-AX45-SAME: "-target-feature" "+m"
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// MCPU-ANDES-AX45-SAME: "-target-feature" "+a"
773-
// MCPU-ANDES-AX45-SAME: "-target-feature" "+f"
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// MCPU-ANDES-AX45-SAME: "-target-feature" "+d"
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// MCPU-ANDES-AX45-SAME: "-target-feature" "+c"
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// MCPU-ANDES-AX45-SAME: "-target-feature" "+zicsr"
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// MCPU-ANDES-AX45-SAME: "-target-feature" "+zifencei"
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// MCPU-ANDES-AX45-SAME: "-target-feature" "+zba"
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// MCPU-ANDES-AX45-SAME: "-target-feature" "+zbb"
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// MCPU-ANDES-AX45-SAME: "-target-feature" "+zbs"
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// MCPU-ANDES-AX45-SAME: "-target-abi" "lp64d"
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// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=andes-ax45 | FileCheck -check-prefix=MTUNE-ANDES-AX45 %s

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