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Yeting Kuo
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clang/docs/ShadowCallStack.rst

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@@ -60,8 +60,10 @@ and destruction would need to be intercepted by the application.
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The instrumentation makes use of the platform register ``x18`` on AArch64,
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``x3`` (``gp``) on RISC-V with software shadow stack and ``ssp`` on RISC-V with
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hardware shadow stack, which needs `Zicfiss`_ and ``-mno-forced-sw-shadow-stack``
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(default option). ``-mforced-sw-shadow-stack`` make risc-v backend generate
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software shadow stack with `Zicfiss`_ when shadow stack enabled.
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(default option). Note that with ``Zicfiss``_ the RISC-V backend will default to
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the hardware based shadow call stack. Users can force the RISC-V backend to
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generate the software shadow call stack with ``Zicfiss``_ by passing
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``-mforced-sw-shadow-stack``.
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For simplicity we will refer to this as the ``SCSReg``. On some platforms,
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``SCSReg`` is reserved, and on others, it is designated as a scratch register.
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This generally means that any code that may run on the same thread as code compiled with ShadowCallStack must either target
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To enable ShadowCallStack, just pass the ``-fsanitize=shadow-call-stack`` flag
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to both compile and link command lines. On aarch64, you also need to pass
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``-ffixed-x18`` unless your target already reserves ``x18``. On RISC-V with software
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shadow stack, ``x3`` (``gp``) is always reserved. It is, however, important to
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disable GP relaxation in the linker. This can be done with the ``--no-relax-gp``
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flag in GNU ld.
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``-ffixed-x18`` unless your target already reserves ``x18``. No additional flags
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need to be passed on RISC-V because the software based shadow stack uses ``x3`` (``gp``),
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which is always reserved, and the hardware based shadow call stack uses a dedicated register, ``ssp``.
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However, it is important to disable GP relaxation in the linker when using the
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software based shadow call stack on RISC-V. This can be done with the
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``--no-relax-gp`` flag in GNU ld, and is off by default in LLD.
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Low-level API
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-------------

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