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[ConstraintElim] Add pre-commit tests for PR82271. NFC. (#82357)
This patch adds some tests for #82344.
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‎llvm/test/Transforms/ConstraintElimination/minmax.ll

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Original file line numberDiff line numberDiff line change
@@ -601,6 +601,126 @@ else:
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ret i32 -1
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}
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define i64 @pr82271(i32 %a, i32 %b){
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; CHECK-LABEL: define i64 @pr82271
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; CHECK-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[A]], [[B]]
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; CHECK-NEXT: br i1 [[CMP]], label [[THEN:%.*]], label [[ELSE:%.*]]
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; CHECK: then:
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; CHECK-NEXT: [[SA:%.*]] = sext i32 [[A]] to i64
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; CHECK-NEXT: [[SB:%.*]] = sext i32 [[B]] to i64
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; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[SA]], 1
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; CHECK-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[SB]], i64 [[ADD]])
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; CHECK-NEXT: ret i64 [[SMAX]]
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; CHECK: else:
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; CHECK-NEXT: ret i64 0
618+
;
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entry:
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%cmp = icmp slt i32 %a, %b
621+
br i1 %cmp, label %then, label %else
622+
623+
then:
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%sa = sext i32 %a to i64
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%sb = sext i32 %b to i64
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%add = add nsw i64 %sa, 1
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%smax = call i64 @llvm.smax.i64(i64 %sb, i64 %add)
628+
ret i64 %smax
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else:
631+
ret i64 0
632+
}
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define i64 @pr82271_sext_zext_nneg(i32 %a, i32 %b){
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; CHECK-LABEL: define i64 @pr82271_sext_zext_nneg
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; CHECK-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[A]], [[B]]
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; CHECK-NEXT: br i1 [[CMP]], label [[THEN:%.*]], label [[ELSE:%.*]]
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; CHECK: then:
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; CHECK-NEXT: [[SA:%.*]] = sext i32 [[A]] to i64
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; CHECK-NEXT: [[SB:%.*]] = zext nneg i32 [[B]] to i64
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; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[SA]], 1
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; CHECK-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[SB]], i64 [[ADD]])
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; CHECK-NEXT: ret i64 [[SMAX]]
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; CHECK: else:
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; CHECK-NEXT: ret i64 0
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;
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entry:
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%cmp = icmp slt i32 %a, %b
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br i1 %cmp, label %then, label %else
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then:
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%sa = sext i32 %a to i64
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%sb = zext nneg i32 %b to i64
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%add = add nsw i64 %sa, 1
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%smax = call i64 @llvm.smax.i64(i64 %sb, i64 %add)
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ret i64 %smax
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else:
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ret i64 0
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}
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define i64 @pr82271_zext_nneg(i32 %a, i32 %b){
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; CHECK-LABEL: define i64 @pr82271_zext_nneg
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; CHECK-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[A]], [[B]]
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; CHECK-NEXT: br i1 [[CMP]], label [[THEN:%.*]], label [[ELSE:%.*]]
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; CHECK: then:
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; CHECK-NEXT: [[SA:%.*]] = zext nneg i32 [[A]] to i64
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; CHECK-NEXT: [[SB:%.*]] = zext nneg i32 [[B]] to i64
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; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[SA]], 1
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; CHECK-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[SB]], i64 [[ADD]])
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; CHECK-NEXT: ret i64 [[SMAX]]
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; CHECK: else:
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; CHECK-NEXT: ret i64 0
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;
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entry:
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%cmp = icmp slt i32 %a, %b
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br i1 %cmp, label %then, label %else
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then:
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%sa = zext nneg i32 %a to i64
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%sb = zext nneg i32 %b to i64
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%add = add nsw i64 %sa, 1
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%smax = call i64 @llvm.smax.i64(i64 %sb, i64 %add)
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ret i64 %smax
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else:
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ret i64 0
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}
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define i64 @pr82271_zext(i32 %a, i32 %b){
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; CHECK-LABEL: define i64 @pr82271_zext
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; CHECK-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[A]], [[B]]
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; CHECK-NEXT: br i1 [[CMP]], label [[THEN:%.*]], label [[ELSE:%.*]]
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; CHECK: then:
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; CHECK-NEXT: [[SA:%.*]] = zext i32 [[A]] to i64
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; CHECK-NEXT: [[SB:%.*]] = zext i32 [[B]] to i64
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; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[SA]], 1
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; CHECK-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[SB]], i64 [[ADD]])
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; CHECK-NEXT: ret i64 [[SMAX]]
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; CHECK: else:
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; CHECK-NEXT: ret i64 0
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;
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entry:
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%cmp = icmp slt i32 %a, %b
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br i1 %cmp, label %then, label %else
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then:
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%sa = zext i32 %a to i64
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%sb = zext i32 %b to i64
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%add = add nsw i64 %sa, 1
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%smax = call i64 @llvm.smax.i64(i64 %sb, i64 %add)
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ret i64 %smax
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else:
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ret i64 0
722+
}
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declare i32 @llvm.smin.i32(i32, i32)
605725
declare i32 @llvm.smax.i32(i32, i32)
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declare i32 @llvm.umin.i32(i32, i32)

‎llvm/test/Transforms/ConstraintElimination/sext.ll

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,218 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
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; RUN: opt -passes=constraint-elimination -S %s | FileCheck %s
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define i1 @cmp_sext(i32 %a, i32 %b){
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; CHECK-LABEL: define i1 @cmp_sext(
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; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]]) {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[A]], [[B]]
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; CHECK-NEXT: br i1 [[CMP]], label [[THEN:%.*]], label [[ELSE:%.*]]
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; CHECK: then:
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; CHECK-NEXT: [[SA:%.*]] = sext i32 [[A]] to i64
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; CHECK-NEXT: [[SB:%.*]] = sext i32 [[B]] to i64
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; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[SA]], 1
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; CHECK-NEXT: [[CMP2:%.*]] = icmp sge i64 [[SB]], [[ADD]]
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; CHECK-NEXT: ret i1 [[CMP2]]
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; CHECK: else:
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; CHECK-NEXT: ret i1 false
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;
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entry:
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%cmp = icmp slt i32 %a, %b
21+
br i1 %cmp, label %then, label %else
22+
23+
then:
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%sa = sext i32 %a to i64
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%sb = sext i32 %b to i64
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%add = add nsw i64 %sa, 1
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%cmp2 = icmp sge i64 %sb, %add
28+
ret i1 %cmp2
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else:
31+
ret i1 false
32+
}
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34+
define i1 @cmp_sext_positive_increment(i32 %a, i32 %b, i64 %c){
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; CHECK-LABEL: define i1 @cmp_sext_positive_increment(
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; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]], i64 [[C:%.*]]) {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[POS:%.*]] = icmp sgt i64 [[C]], 0
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; CHECK-NEXT: call void @llvm.assume(i1 [[POS]])
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; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[A]], [[B]]
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; CHECK-NEXT: br i1 [[CMP]], label [[THEN:%.*]], label [[ELSE:%.*]]
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; CHECK: then:
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; CHECK-NEXT: [[SA:%.*]] = sext i32 [[A]] to i64
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; CHECK-NEXT: [[SB:%.*]] = sext i32 [[B]] to i64
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; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[SA]], [[C]]
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; CHECK-NEXT: [[CMP2:%.*]] = icmp sge i64 [[SB]], [[ADD]]
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; CHECK-NEXT: ret i1 [[CMP2]]
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; CHECK: else:
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; CHECK-NEXT: ret i1 false
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;
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entry:
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%pos = icmp sgt i64 %c, 0
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call void @llvm.assume(i1 %pos)
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%cmp = icmp slt i32 %a, %b
55+
br i1 %cmp, label %then, label %else
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then:
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%sa = sext i32 %a to i64
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%sb = sext i32 %b to i64
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%add = add nsw i64 %sa, %c
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%cmp2 = icmp sge i64 %sb, %add
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ret i1 %cmp2
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else:
65+
ret i1 false
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}
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define i1 @cmp_sext_sgt(i32 %a, i32 %b){
69+
; CHECK-LABEL: define i1 @cmp_sext_sgt(
70+
; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]]) {
71+
; CHECK-NEXT: entry:
72+
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[A]], [[B]]
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; CHECK-NEXT: br i1 [[CMP]], label [[THEN:%.*]], label [[ELSE:%.*]]
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; CHECK: then:
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; CHECK-NEXT: [[SA:%.*]] = sext i32 [[A]] to i64
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; CHECK-NEXT: [[SB:%.*]] = sext i32 [[B]] to i64
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; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[SA]], 1
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; CHECK-NEXT: [[CMP2:%.*]] = icmp sgt i64 [[SB]], [[ADD]]
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; CHECK-NEXT: ret i1 [[CMP2]]
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; CHECK: else:
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; CHECK-NEXT: ret i1 false
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;
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entry:
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%cmp = icmp slt i32 %a, %b
85+
br i1 %cmp, label %then, label %else
86+
87+
then:
88+
%sa = sext i32 %a to i64
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%sb = sext i32 %b to i64
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%add = add nsw i64 %sa, 1
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%cmp2 = icmp sgt i64 %sb, %add
92+
ret i1 %cmp2
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94+
else:
95+
ret i1 false
96+
}
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98+
define i1 @cmp_zext_nneg(i32 %a, i32 %b){
99+
; CHECK-LABEL: define i1 @cmp_zext_nneg(
100+
; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]]) {
101+
; CHECK-NEXT: entry:
102+
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[A]], [[B]]
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; CHECK-NEXT: br i1 [[CMP]], label [[THEN:%.*]], label [[ELSE:%.*]]
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; CHECK: then:
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; CHECK-NEXT: [[SA:%.*]] = zext nneg i32 [[A]] to i64
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; CHECK-NEXT: [[SB:%.*]] = zext nneg i32 [[B]] to i64
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; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[SA]], 1
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; CHECK-NEXT: [[CMP2:%.*]] = icmp sge i64 [[SB]], [[ADD]]
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; CHECK-NEXT: ret i1 [[CMP2]]
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; CHECK: else:
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; CHECK-NEXT: ret i1 false
112+
;
113+
entry:
114+
%cmp = icmp slt i32 %a, %b
115+
br i1 %cmp, label %then, label %else
116+
117+
then:
118+
%sa = zext nneg i32 %a to i64
119+
%sb = zext nneg i32 %b to i64
120+
%add = add nsw i64 %sa, 1
121+
%cmp2 = icmp sge i64 %sb, %add
122+
ret i1 %cmp2
123+
124+
else:
125+
ret i1 false
126+
}
127+
128+
; Negative tests
129+
130+
define i1 @cmp_sext_unsigned(i32 %a, i32 %b){
131+
; CHECK-LABEL: define i1 @cmp_sext_unsigned(
132+
; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]]) {
133+
; CHECK-NEXT: entry:
134+
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[A]], [[B]]
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; CHECK-NEXT: br i1 [[CMP]], label [[THEN:%.*]], label [[ELSE:%.*]]
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; CHECK: then:
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; CHECK-NEXT: [[SA:%.*]] = sext i32 [[A]] to i64
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; CHECK-NEXT: [[SB:%.*]] = sext i32 [[B]] to i64
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; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[SA]], 1
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; CHECK-NEXT: [[CMP2:%.*]] = icmp uge i64 [[SB]], [[ADD]]
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; CHECK-NEXT: ret i1 [[CMP2]]
142+
; CHECK: else:
143+
; CHECK-NEXT: ret i1 false
144+
;
145+
entry:
146+
%cmp = icmp slt i32 %a, %b
147+
br i1 %cmp, label %then, label %else
148+
149+
then:
150+
%sa = sext i32 %a to i64
151+
%sb = sext i32 %b to i64
152+
%add = add nsw i64 %sa, 1
153+
%cmp2 = icmp uge i64 %sb, %add
154+
ret i1 %cmp2
155+
156+
else:
157+
ret i1 false
158+
}
159+
160+
define i1 @cmp_zext(i32 %a, i32 %b){
161+
; CHECK-LABEL: define i1 @cmp_zext(
162+
; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]]) {
163+
; CHECK-NEXT: entry:
164+
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[A]], [[B]]
165+
; CHECK-NEXT: br i1 [[CMP]], label [[THEN:%.*]], label [[ELSE:%.*]]
166+
; CHECK: then:
167+
; CHECK-NEXT: [[SA:%.*]] = zext i32 [[A]] to i64
168+
; CHECK-NEXT: [[SB:%.*]] = zext i32 [[B]] to i64
169+
; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[SA]], 1
170+
; CHECK-NEXT: [[CMP2:%.*]] = icmp sge i64 [[SB]], [[ADD]]
171+
; CHECK-NEXT: ret i1 [[CMP2]]
172+
; CHECK: else:
173+
; CHECK-NEXT: ret i1 false
174+
;
175+
entry:
176+
%cmp = icmp slt i32 %a, %b
177+
br i1 %cmp, label %then, label %else
178+
179+
then:
180+
%sa = zext i32 %a to i64
181+
%sb = zext i32 %b to i64
182+
%add = add nsw i64 %sa, 1
183+
%cmp2 = icmp sge i64 %sb, %add
184+
ret i1 %cmp2
185+
186+
else:
187+
ret i1 false
188+
}
189+
190+
define i1 @cmp_sext_unknown_increment(i32 %a, i32 %b, i64 %c){
191+
; CHECK-LABEL: define i1 @cmp_sext_unknown_increment(
192+
; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]], i64 [[C:%.*]]) {
193+
; CHECK-NEXT: entry:
194+
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[A]], [[B]]
195+
; CHECK-NEXT: br i1 [[CMP]], label [[THEN:%.*]], label [[ELSE:%.*]]
196+
; CHECK: then:
197+
; CHECK-NEXT: [[SA:%.*]] = sext i32 [[A]] to i64
198+
; CHECK-NEXT: [[SB:%.*]] = sext i32 [[B]] to i64
199+
; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[SA]], [[C]]
200+
; CHECK-NEXT: [[CMP2:%.*]] = icmp sge i64 [[SB]], [[ADD]]
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; CHECK-NEXT: ret i1 [[CMP2]]
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; CHECK: else:
203+
; CHECK-NEXT: ret i1 false
204+
;
205+
entry:
206+
%cmp = icmp slt i32 %a, %b
207+
br i1 %cmp, label %then, label %else
208+
209+
then:
210+
%sa = sext i32 %a to i64
211+
%sb = sext i32 %b to i64
212+
%add = add nsw i64 %sa, %c
213+
%cmp2 = icmp sge i64 %sb, %add
214+
ret i1 %cmp2
215+
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else:
217+
ret i1 false
218+
}

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