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Revert "[SME] Add intrinsics for FCVT(wid.) and FCVTL" (#93196)
Reverts #90215
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‎clang/include/clang/Basic/arm_sve.td

Lines changed: 0 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -2265,10 +2265,6 @@ let TargetGuard = "sme2" in {
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def SVCVT_S32_F32_X4 : SInst<"svcvt_{d}[_f32_x4]", "4.d4.M", "i", MergeNone, "aarch64_sve_fcvtzs_x4", [IsStreaming, IsOverloadWhileOrMultiVecCvt], []>;
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}
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2268-
let TargetGuard = "sme-f16f16" in {
2269-
def SVCVT_F32_X2 : SInst<"svcvt_{d}[_f16_x2]", "2h", "f", MergeNone, "aarch64_sve_fcvt_widen_x2", [ IsStreaming],[]>;
2270-
}
2271-
22722268
//
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// Multi-vector floating-point convert from single-precision to interleaved half-precision/BFloat16
22742270
//
@@ -2277,13 +2273,6 @@ let TargetGuard = "sme2" in {
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def SVCVTN_BF16_X2 : SInst<"svcvtn_bf16[_f32_x2]", "$2", "f", MergeNone, "aarch64_sve_bfcvtn_x2", [IsOverloadNone, IsStreaming],[]>;
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}
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2280-
//
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//Multi-vector floating-point convert from half-precision to deinterleaved single-precision.
2282-
//
2283-
let TargetGuard = "sme-f16f16" in {
2284-
def SVCVTL_F32_X2 : SInst<"svcvtl_f32[_f16_x2]", "2h", "f", MergeNone, "aarch64_sve_fcvtl_widen_x2", [ IsStreaming],[]>;
2285-
}
2286-
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//
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// Multi-vector saturating extract narrow
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//

‎clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvt.c

Lines changed: 0 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -497,25 +497,3 @@ svuint8_t test_qcvt_u8_s32_x4(svint32x4_t zn) __arm_streaming {
497497
svuint16_t test_qcvt_u16_s64_x4(svint64x4_t zn) __arm_streaming {
498498
return SVE_ACLE_FUNC(svqcvt_u16,_s64_x4,,)(zn);
499499
}
500-
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// CHECK-LABEL: @test_cvt_f32_x2(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.fcvt.widen.x2.nxv4f32(<vscale x 8 x half> [[ZN:%.*]])
504-
// CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } [[TMP0]], 0
505-
// CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv4f32(<vscale x 8 x float> poison, <vscale x 4 x float> [[TMP1]], i64 0)
506-
// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } [[TMP0]], 1
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// CHECK-NEXT: [[TMP4:%.*]] = tail call <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv4f32(<vscale x 8 x float> [[TMP2]], <vscale x 4 x float> [[TMP3]], i64 4)
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// CHECK-NEXT: ret <vscale x 8 x float> [[TMP4]]
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//
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// CPP-CHECK-LABEL: @_Z15test_cvt_f32_x2u13__SVFloat16_t(
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// CPP-CHECK-NEXT: entry:
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// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.fcvt.widen.x2.nxv4f32(<vscale x 8 x half> [[ZN:%.*]])
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// CPP-CHECK-NEXT: [[TMP1:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } [[TMP0]], 0
514-
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv4f32(<vscale x 8 x float> poison, <vscale x 4 x float> [[TMP1]], i64 0)
515-
// CPP-CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <vscale x 4 x float>, <vscale x 4 x float> } [[TMP0]], 1
516-
// CPP-CHECK-NEXT: [[TMP4:%.*]] = tail call <vscale x 8 x float> @llvm.vector.insert.nxv8f32.nxv4f32(<vscale x 8 x float> [[TMP2]], <vscale x 4 x float> [[TMP3]], i64 4)
517-
// CPP-CHECK-NEXT: ret <vscale x 8 x float> [[TMP4]]
518-
//
519-
__attribute__((target("sme-f16f16"))) svfloat32x2_t test_cvt_f32_x2(svfloat16_t zn) __arm_streaming {
520-
return SVE_ACLE_FUNC(svcvt_f32,_f16_x2,,)(zn);
521-
}

‎clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvtl.c

Lines changed: 0 additions & 40 deletions
This file was deleted.

‎llvm/include/llvm/IR/IntrinsicsAArch64.td

Lines changed: 1 addition & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -3121,11 +3121,6 @@ let TargetPrefix = "aarch64" in {
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: DefaultAttrsIntrinsic<[llvm_nxv8bf16_ty],
31223122
[llvm_nxv4f32_ty, llvm_nxv4f32_ty],
31233123
[IntrNoMem]>;
3124-
3125-
class SME2_CVT_WIDENING_VG2_Intrinsic
3126-
: DefaultAttrsIntrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
3127-
[LLVMSubdivide2VectorType<0>], [IntrNoMem]>;
3128-
31293124

31303125
class SME2_CVT_VG4_SINGLE_Intrinsic
31313126
: DefaultAttrsIntrinsic<[LLVMSubdivide4VectorType<0>],
@@ -3417,13 +3412,6 @@ let TargetPrefix = "aarch64" in {
34173412
def int_aarch64_sme_suvdot_lane_za32_vg1x4 : SME2_Matrix_ArrayVector_VG4_Multi_Index_Intrinsic;
34183413
def int_aarch64_sme_usvdot_lane_za32_vg1x4 : SME2_Matrix_ArrayVector_VG4_Multi_Index_Intrinsic;
34193414

3420-
3421-
//
3422-
//Multi-vector floating-point convert from half-precision to deinterleaved single-precision.
3423-
//
3424-
3425-
def int_aarch64_sve_fcvtl_widen_x2 : SME2_CVT_WIDENING_VG2_Intrinsic;
3426-
34273415
//
34283416
// Multi-vector floating-point CVT from single-precision to interleaved half-precision/BFloat16
34293417
//
@@ -3443,7 +3431,7 @@ let TargetPrefix = "aarch64" in {
34433431
def int_aarch64_sve_fcvtzu_x4 : SME2_CVT_X4_Intrinsic;
34443432
def int_aarch64_sve_scvtf_x4 : SME2_CVT_X4_Intrinsic;
34453433
def int_aarch64_sve_ucvtf_x4 : SME2_CVT_X4_Intrinsic;
3446-
def int_aarch64_sve_fcvt_widen_x2 : SME2_CVT_WIDENING_VG2_Intrinsic;
3434+
34473435
//
34483436
// Multi-vector saturating extract narrow
34493437
//

‎llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

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Original file line numberDiff line numberDiff line change
@@ -5717,12 +5717,6 @@ void AArch64DAGToDAGISel::Select(SDNode *Node) {
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case Intrinsic::aarch64_sve_ucvtf_x4:
57185718
SelectCVTIntrinsic(Node, 4, AArch64::UCVTF_4Z4Z_StoS);
57195719
return;
5720-
case Intrinsic::aarch64_sve_fcvt_widen_x2:
5721-
SelectUnaryMultiIntrinsic(Node, 2, false, AArch64::FCVT_2ZZ_H_S);
5722-
return;
5723-
case Intrinsic::aarch64_sve_fcvtl_widen_x2:
5724-
SelectUnaryMultiIntrinsic(Node, 2, false, AArch64::FCVTL_2ZZ_H_S);
5725-
return;
57265720
case Intrinsic::aarch64_sve_sclamp_single_x2:
57275721
if (auto Op = SelectOpcodeFromVT<SelectTypeKind::Int>(
57285722
Node->getValueType(0),

‎llvm/test/CodeGen/AArch64/sme2-intrinsics-cvt.ll

Lines changed: 1 addition & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme-f16f16 -verify-machineinstrs < %s | FileCheck %s
2+
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 -verify-machineinstrs < %s | FileCheck %s
33

44
;
55
; FCVT
@@ -139,15 +139,6 @@ define {<vscale x 4 x float>, <vscale x 4 x float>,<vscale x 4 x float>, <vscale
139139
ret {<vscale x 4 x float>, <vscale x 4 x float>,<vscale x 4 x float>, <vscale x 4 x float>} %res
140140
}
141141

142-
define {<vscale x 4 x float>, <vscale x 4 x float>} @multi_vector_cvt_widen_x2_f16(<vscale x 8 x half> %zn0) {
143-
; CHECK-LABEL: multi_vector_cvt_widen_x2_f16:
144-
; CHECK: // %bb.0:
145-
; CHECK-NEXT: fcvt { z0.s, z1.s }, z0.h
146-
; CHECK-NEXT: ret
147-
%res = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.fcvt.widen.x2.nxv4f32(<vscale x 8 x half> %zn0)
148-
ret {<vscale x 4 x float>, <vscale x 4 x float>} %res
149-
}
150-
151142
declare <vscale x 8 x half> @llvm.aarch64.sve.fcvt.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>)
152143
declare <vscale x 8 x bfloat> @llvm.aarch64.sve.bfcvt.x2(<vscale x 4 x float>, <vscale x 4 x float>)
153144
declare {<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.aarch64.sve.fcvtzs.x2.nxv4i32.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>)

‎llvm/test/CodeGen/AArch64/sme2-intrinsics-cvtl.ll

Lines changed: 0 additions & 11 deletions
This file was deleted.

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