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[RISCV] Add Sched classes for vector crypto instructions
The vector crypto instructions may have different scheduling behavior compared to VALU operations. Instead of using scheduling resources that describe VALU operations, we give these instructions their own scheduling resources. This is similar to what we did for Zb* instructions. The sifive-p670 has vector crypto, so we model behavior for these instructions in the P600SchedModel. The numbers are based off of measurements collected internally. These numbers are a bit old and new measurments show that they may not be fully accurate. It is likley that we will refine these numbers in a follow up patch(s) based on new measurments.
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12 files changed

+498
-133
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‎llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td

Lines changed: 110 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -24,9 +24,9 @@ def tuimm5 : RISCVOp, TImmLeaf<XLenVT, [{return isUInt<5>(Imm);}]>;
2424
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
2525
multiclass VCLMUL_MV_V_X<string opcodestr, bits<6> funct6> {
2626
def V : VALUVV<funct6, OPMVV, opcodestr # "." # "vv">,
27-
SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">;
27+
SchedBinaryMC<"WriteVCLMUL", "ReadVCLMUL", "ReadVCLMUL">;
2828
def X : VALUVX<funct6, OPMVX, opcodestr # "." # "vx">,
29-
SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">;
29+
SchedBinaryMC<"WriteVCLMULH", "ReadVCLMULH", "ReadVCLMULH">;
3030
}
3131

3232
class RVInstIVI_VROR<bits<6> funct6, dag outs, dag ins, string opcodestr,
@@ -55,7 +55,7 @@ multiclass VROR_IV_V_X_I<string opcodestr, bits<6> funct6>
5555
def I : RVInstIVI_VROR<funct6, (outs VR:$vd),
5656
(ins VR:$vs2, uimm6:$imm, VMaskOp:$vm),
5757
opcodestr # ".vi", "$vd, $vs2, $imm$vm">,
58-
SchedUnaryMC<"WriteVIALUI", "ReadVIALUV">;
58+
SchedUnaryMC<"WriteVROR", "ReadVROR">;
5959
}
6060

6161
// op vd, vs2, vs1
@@ -107,10 +107,10 @@ multiclass VAES_MV_V_S<bits<6> funct6_vv, bits<6> funct6_vs, bits<5> vs1,
107107
RISCVVFormat opv, string opcodestr> {
108108
let RVVConstraint = NoConstraint in
109109
def NAME # _VV : PALUVs2NoVmBinary<funct6_vv, vs1, opv, opcodestr # ".vv">,
110-
SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">;
110+
SchedBinaryMC<"WriteVAESMV", "ReadVAESMV", "ReadVAESMV">;
111111
let RVVConstraint = VS2Constraint in
112112
def NAME # _VS : PALUVs2NoVmBinary<funct6_vs, vs1, opv, opcodestr # ".vs">,
113-
SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">;
113+
SchedBinaryMC<"WriteVAESMV", "ReadVAESMV", "ReadVAESMV">;
114114
}
115115
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
116116

@@ -142,22 +142,22 @@ let Predicates = [HasStdExtZvkb] in {
142142

143143
let Predicates = [HasStdExtZvkg], RVVConstraint = NoConstraint in {
144144
def VGHSH_VV : PALUVVNoVmTernary<0b101100, OPMVV, "vghsh.vv">,
145-
SchedTernaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV",
146-
"ReadVIALUV">;
145+
SchedTernaryMC<"WriteVGHSH", "ReadVGHSH", "ReadVGHSH",
146+
"ReadVGHSH">;
147147
def VGMUL_VV : PALUVs2NoVmBinary<0b101000, 0b10001, OPMVV, "vgmul.vv">,
148-
SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">;
148+
SchedBinaryMC<"WriteVGMUL", "ReadVGMUL", "ReadVGMUL">;
149149
} // Predicates = [HasStdExtZvkg]
150150

151151
let Predicates = [HasStdExtZvknhaOrZvknhb], RVVConstraint = Sha2Constraint in {
152152
def VSHA2CH_VV : PALUVVNoVmTernary<0b101110, OPMVV, "vsha2ch.vv">,
153-
SchedTernaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV",
154-
"ReadVIALUV">;
153+
SchedTernaryMC<"WriteVSHA2CH", "ReadVSHA2CH", "ReadVSHA2CH",
154+
"ReadVSHA2CH">;
155155
def VSHA2CL_VV : PALUVVNoVmTernary<0b101111, OPMVV, "vsha2cl.vv">,
156-
SchedTernaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV",
157-
"ReadVIALUV">;
156+
SchedTernaryMC<"WriteVSHA2CL", "ReadVSHA2CL", "ReadVSHA2CL",
157+
"ReadVSHA2CL">;
158158
def VSHA2MS_VV : PALUVVNoVmTernary<0b101101, OPMVV, "vsha2ms.vv">,
159-
SchedTernaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV",
160-
"ReadVIALUV">;
159+
SchedTernaryMC<"WriteVSHA2MS", "ReadVSHA2MS", "ReadVSHA2MS",
160+
"ReadVSHA2MS">;
161161
} // Predicates = [HasStdExtZvknhaOrZvknhb]
162162

163163
let Predicates = [HasStdExtZvkned] in {
@@ -166,26 +166,26 @@ let Predicates = [HasStdExtZvkned] in {
166166
defm VAESEF : VAES_MV_V_S<0b101000, 0b101001, 0b00011, OPMVV, "vaesef">;
167167
defm VAESEM : VAES_MV_V_S<0b101000, 0b101001, 0b00010, OPMVV, "vaesem">;
168168
def VAESKF1_VI : PALUVINoVm<0b100010, "vaeskf1.vi", uimm5>,
169-
SchedUnaryMC<"WriteVIALUV", "ReadVIALUV">;
169+
SchedUnaryMC<"WriteVAESKF1", "ReadVAESKF2">;
170170
def VAESKF2_VI : PALUVINoVmBinary<0b101010, "vaeskf2.vi", uimm5>,
171-
SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">;
171+
SchedBinaryMC<"WriteVAESKF2", "ReadVAESKF2", "ReadVAESKF2">;
172172
let RVVConstraint = VS2Constraint in
173173
def VAESZ_VS : PALUVs2NoVmBinary<0b101001, 0b00111, OPMVV, "vaesz.vs">,
174-
SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">;
174+
SchedBinaryMC<"WriteVAESZ", "ReadVAESZ", "ReadVAESZ">;
175175
} // Predicates = [HasStdExtZvkned]
176176

177177
let Predicates = [HasStdExtZvksed] in {
178178
let RVVConstraint = NoConstraint in
179179
def VSM4K_VI : PALUVINoVm<0b100001, "vsm4k.vi", uimm5>,
180-
SchedUnaryMC<"WriteVIALUV", "ReadVIALUV">;
180+
SchedUnaryMC<"WriteVSM4K", "ReadVSM4K">;
181181
defm VSM4R : VAES_MV_V_S<0b101000, 0b101001, 0b10000, OPMVV, "vsm4r">;
182182
} // Predicates = [HasStdExtZvksed]
183183

184184
let Predicates = [HasStdExtZvksh], RVVConstraint = VS2Constraint in {
185185
def VSM3C_VI : PALUVINoVmBinary<0b101011, "vsm3c.vi", uimm5>,
186-
SchedBinaryMC<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV">;
186+
SchedBinaryMC<"WriteVSM3C", "ReadVSM3C", "ReadVSM3C">;
187187
def VSM3ME_VV : PALUVVNoVm<0b100000, OPMVV, "vsm3me.vv">,
188-
SchedUnaryMC<"WriteVIALUI", "ReadVIALUV">;
188+
SchedUnaryMC<"WriteVSM3ME", "ReadVSM3ME">;
189189
} // Predicates = [HasStdExtZvksh]
190190

191191
//===----------------------------------------------------------------------===//
@@ -337,10 +337,10 @@ multiclass VPseudoVCLMUL_VV_VX {
337337
foreach m = MxList in {
338338
defvar mx = m.MX;
339339
defm "" : VPseudoBinaryV_VV<m>,
340-
SchedBinary<"WriteVIALUV", "ReadVIALUV", "ReadVIALUV", mx,
340+
SchedBinary<"WriteVCLMUL", "ReadVCLMUL", "ReadVCLMUL", mx,
341341
forceMergeOpRead=true>;
342342
defm "" : VPseudoBinaryV_VX<m>,
343-
SchedBinary<"WriteVIALUX", "ReadVIALUV", "ReadVIALUX", mx,
343+
SchedBinary<"WriteVCLMULH", "ReadVCLMULH", "ReadVCLMULH", mx,
344344
forceMergeOpRead=true>;
345345
}
346346
}
@@ -354,28 +354,104 @@ multiclass VPseudoUnaryV_V<LMULInfo m> {
354354
}
355355
}
356356

357-
multiclass VPseudoVALU_V {
357+
multiclass VPseudoVBREV {
358358
foreach m = MxList in {
359359
defvar mx = m.MX;
360360
defm "" : VPseudoUnaryV_V<m>,
361-
SchedUnary<"WriteVIALUV", "ReadVIALUV", mx,
362-
forceMergeOpRead=true>;
361+
SchedUnary<"WriteVBREV", "ReadVBREV", mx, forceMergeOpRead=true>;
362+
}
363+
}
364+
365+
multiclass VPseudoVCLZ {
366+
foreach m = MxList in {
367+
defvar mx = m.MX;
368+
defm "" : VPseudoUnaryV_V<m>,
369+
SchedUnary<"WriteVCLZ", "ReadVCLZ", mx, forceMergeOpRead=true>;
370+
}
371+
}
372+
373+
multiclass VPseudoVCTZ {
374+
foreach m = MxList in {
375+
defvar mx = m.MX;
376+
defm "" : VPseudoUnaryV_V<m>,
377+
SchedUnary<"WriteVCTZ", "ReadVCTZ", mx, forceMergeOpRead=true>;
378+
}
379+
}
380+
381+
multiclass VPseudoVCPOP {
382+
foreach m = MxList in {
383+
defvar mx = m.MX;
384+
defm "" : VPseudoUnaryV_V<m>,
385+
SchedUnary<"WriteVCPOP", "ReadVCPOP", mx, forceMergeOpRead=true>;
363386
}
364387
}
365388

366389
multiclass VPseudoVWALU_VV_VX_VI<Operand ImmType> : VPseudoVWALU_VV_VX {
367390
foreach m = MxListW in {
368391
defm "" : VPseudoBinaryW_VI<ImmType, m>,
369-
SchedUnary<"WriteVIWALUV", "ReadVIWALUV", m.MX,
392+
SchedUnary<"WriteVWSLL", "ReadVWSLL", m.MX,
370393
forceMergeOpRead=true>;
371394
}
372395
}
373396

397+
multiclass VPseudoVANDN {
398+
foreach m = MxList in {
399+
defm "" : VPseudoBinaryV_VV<m>,
400+
SchedBinary<"WriteVANDN", "ReadVANDN", "ReadVANDN", m.MX,
401+
forceMergeOpRead=true>;
402+
defm "" : VPseudoBinaryV_VX<m>,
403+
SchedBinary<"WriteVANDN", "ReadVANDN", "ReadVANDN", m.MX,
404+
forceMergeOpRead=true>;
405+
}
406+
}
407+
408+
multiclass VPseudoVBREV8 {
409+
foreach m = MxList in {
410+
defvar mx = m.MX;
411+
defm "" : VPseudoUnaryV_V<m>,
412+
SchedUnary<"WriteVBREV8", "ReadVBREV8", mx, forceMergeOpRead=true>;
413+
}
414+
}
415+
416+
multiclass VPseudoVREV8 {
417+
foreach m = MxList in {
418+
defvar mx = m.MX;
419+
defm "" : VPseudoUnaryV_V<m>,
420+
SchedUnary<"WriteVREV8", "ReadVREV8", mx, forceMergeOpRead=true>;
421+
}
422+
}
423+
424+
multiclass VPseudoVROL {
425+
foreach m = MxList in {
426+
defm "" : VPseudoBinaryV_VV<m>,
427+
SchedBinary<"WriteVROL", "ReadVROL", "ReadVROL", m.MX,
428+
forceMergeOpRead=true>;
429+
defm "" : VPseudoBinaryV_VX<m>,
430+
SchedBinary<"WriteVROL", "ReadVROL", "ReadVROL", m.MX,
431+
forceMergeOpRead=true>;
432+
}
433+
}
434+
435+
multiclass VPseudoVROR<Operand ImmType> {
436+
defvar Constraint = "";
437+
foreach m = MxList in {
438+
defvar mx = m.MX;
439+
defm "" : VPseudoBinaryV_VV<m>,
440+
SchedBinary<"WriteVROR", "ReadVROR", "ReadVROR", mx,
441+
forceMergeOpRead=true>;
442+
defm "" : VPseudoBinaryV_VX<m>,
443+
SchedBinary<"WriteVROR", "ReadVROR", "ReadVROR", mx,
444+
forceMergeOpRead=true>;
445+
defm "" : VPseudoBinaryV_VI<ImmType, m>,
446+
SchedUnary<"WriteVROR", "ReadVROR", mx, forceMergeOpRead=true>;
447+
}
448+
}
449+
374450
let Predicates = [HasStdExtZvbb] in {
375-
defm PseudoVBREV : VPseudoVALU_V;
376-
defm PseudoVCLZ : VPseudoVALU_V;
377-
defm PseudoVCTZ : VPseudoVALU_V;
378-
defm PseudoVCPOP : VPseudoVALU_V;
451+
defm PseudoVBREV : VPseudoVBREV;
452+
defm PseudoVCLZ : VPseudoVCLZ;
453+
defm PseudoVCTZ : VPseudoVCTZ;
454+
defm PseudoVCPOP : VPseudoVCPOP;
379455
defm PseudoVWSLL : VPseudoVWALU_VV_VX_VI<uimm5>;
380456
} // Predicates = [HasStdExtZvbb]
381457

@@ -385,10 +461,10 @@ let Predicates = [HasStdExtZvbc] in {
385461
} // Predicates = [HasStdExtZvbc]
386462

387463
let Predicates = [HasStdExtZvkb] in {
388-
defm PseudoVANDN : VPseudoVALU_VV_VX;
389-
defm PseudoVBREV8 : VPseudoVALU_V;
390-
defm PseudoVREV8 : VPseudoVALU_V;
391-
defm PseudoVROL : VPseudoVALU_VV_VX;
464+
defm PseudoVANDN : VPseudoVANDN;
465+
defm PseudoVBREV8 : VPseudoVBREV8;
466+
defm PseudoVREV8 : VPseudoVREV8;
467+
defm PseudoVROL : VPseudoVROL;
392468
defm PseudoVROR : VPseudoVALU_VV_VX_VI<uimm6>;
393469
} // Predicates = [HasStdExtZvkb]
394470

‎llvm/lib/Target/RISCV/RISCVSchedRocket.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -262,4 +262,5 @@ defm : UnsupportedSchedZfa;
262262
defm : UnsupportedSchedZfh;
263263
defm : UnsupportedSchedSFB;
264264
defm : UnsupportedSchedXsfvcp;
265+
defm : UnsupportedSchedZvk;
265266
}

‎llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1298,4 +1298,5 @@ defm : UnsupportedSchedZbc;
12981298
defm : UnsupportedSchedZbkb;
12991299
defm : UnsupportedSchedZbkx;
13001300
defm : UnsupportedSchedZfa;
1301+
defm : UnsupportedSchedZvk;
13011302
}

‎llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -367,4 +367,5 @@ defm : UnsupportedSchedSFB;
367367
defm : UnsupportedSchedZfa;
368368
defm : UnsupportedSchedV;
369369
defm : UnsupportedSchedXsfvcp;
370+
defm : UnsupportedSchedZvk;
370371
}

‎llvm/lib/Target/RISCV/RISCVSchedSiFiveP600.td

Lines changed: 81 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -748,6 +748,60 @@ foreach mx = SchedMxList in {
748748
}
749749
}
750750

751+
// Vector Crypto
752+
foreach mx = SchedMxList in {
753+
defvar LMulLat = SiFiveP600GetLMulCycles<mx>.c;
754+
defvar IsWorstCase = SiFiveP600IsWorstCaseMX<mx, SchedMxList>.c;
755+
// Zvbb
756+
let Latency = 2, ReleaseAtCycles = [LMulLat] in {
757+
defm "" : LMULWriteResMX<"WriteVBREV", [SiFiveP600VectorArith], mx, IsWorstCase>;
758+
defm "" : LMULWriteResMX<"WriteVCLZ", [SiFiveP600VectorArith], mx, IsWorstCase>;
759+
defm "" : LMULWriteResMX<"WriteVCPOP", [SiFiveP600VectorArith], mx, IsWorstCase>;
760+
defm "" : LMULWriteResMX<"WriteVCTZ", [SiFiveP600VectorArith], mx, IsWorstCase>;
761+
defm "" : LMULWriteResMX<"WriteVWSLL", [SiFiveP600VectorArith], mx, IsWorstCase>;
762+
}
763+
// Zvbc
764+
let Latency = 2, ReleaseAtCycles = [LMulLat] in {
765+
defm "" : LMULWriteResMX<"WriteVCLMUL", [SiFiveP600VectorArith], mx, IsWorstCase>;
766+
defm "" : LMULWriteResMX<"WriteVCLMULH", [SiFiveP600VectorArith], mx, IsWorstCase>;
767+
}
768+
// Zvkb
769+
let Latency = 1, ReleaseAtCycles = [LMulLat] in
770+
defm "" : LMULWriteResMX<"WriteVANDN", [SiFiveP600VectorArith], mx, IsWorstCase>;
771+
let Latency = 2, ReleaseAtCycles = [LMulLat] in {
772+
defm "" : LMULWriteResMX<"WriteVBREV8", [SiFiveP600VectorArith], mx, IsWorstCase>;
773+
defm "" : LMULWriteResMX<"WriteVREV8", [SiFiveP600VectorArith], mx, IsWorstCase>;
774+
defm "" : LMULWriteResMX<"WriteVROL", [SiFiveP600VectorArith], mx, IsWorstCase>;
775+
defm "" : LMULWriteResMX<"WriteVROR", [SiFiveP600VectorArith], mx, IsWorstCase>;
776+
}
777+
// Zvkg
778+
let Latency = 2, ReleaseAtCycles = [LMulLat] in {
779+
defm "" : LMULWriteResMX<"WriteVGHSH", [SiFiveP600VectorArith], mx, IsWorstCase>;
780+
defm "" : LMULWriteResMX<"WriteVGMUL", [SiFiveP600VectorArith], mx, IsWorstCase>;
781+
}
782+
// ZvknhaOrZvknhb
783+
let Latency = 3, ReleaseAtCycles = [LMulLat] in {
784+
defm "" : LMULWriteResMX<"WriteVSHA2CH", [SiFiveP600VectorArith], mx, IsWorstCase>;
785+
defm "" : LMULWriteResMX<"WriteVSHA2CL", [SiFiveP600VectorArith], mx, IsWorstCase>;
786+
defm "" : LMULWriteResMX<"WriteVSHA2MS", [SiFiveP600VectorArith], mx, IsWorstCase>;
787+
}
788+
// Zvkned
789+
let Latency = 2, ReleaseAtCycles = [LMulLat] in {
790+
defm "" : LMULWriteResMX<"WriteVAESMV", [SiFiveP600VectorArith], mx, IsWorstCase>;
791+
defm "" : LMULWriteResMX<"WriteVAESKF1", [SiFiveP600VectorArith], mx, IsWorstCase>;
792+
defm "" : LMULWriteResMX<"WriteVAESKF2", [SiFiveP600VectorArith], mx, IsWorstCase>;
793+
}
794+
let Latency = 1, ReleaseAtCycles = [LMulLat] in
795+
defm "" : LMULWriteResMX<"WriteVAESZ", [SiFiveP600VectorArith], mx, IsWorstCase>;
796+
// Zvksed
797+
let Latency = 3, ReleaseAtCycles = [LMulLat] in {
798+
defm "" : LMULWriteResMX<"WriteVSM4K", [SiFiveP600VEXQ0], mx, IsWorstCase>;
799+
defm "" : LMULWriteResMX<"WriteVSM4R", [SiFiveP600VEXQ0], mx, IsWorstCase>;
800+
defm "" : LMULWriteResMX<"WriteVSM3C", [SiFiveP600VEXQ0], mx, IsWorstCase>;
801+
defm "" : LMULWriteResMX<"WriteVSM3ME", [SiFiveP600VEXQ0], mx, IsWorstCase>;
802+
}
803+
}
804+
751805
// Others
752806
def : WriteRes<WriteCSR, [SiFiveP600SYS]>;
753807
def : WriteRes<WriteNop, []>;
@@ -1032,6 +1086,33 @@ foreach mx = SchedMxList in {
10321086
def : ReadAdvance<!cast<SchedRead>("ReadVMergeOp_" # mx # "_E" # sew), 0>;
10331087
}
10341088

1089+
// Vector Crypto Extensions
1090+
defm "" : LMULReadAdvance<"ReadVBREV", 0>;
1091+
defm "" : LMULReadAdvance<"ReadVCLZ", 0>;
1092+
defm "" : LMULReadAdvance<"ReadVCPOP", 0>;
1093+
defm "" : LMULReadAdvance<"ReadVCTZ", 0>;
1094+
defm "" : LMULReadAdvance<"ReadVWSLL", 0>;
1095+
defm "" : LMULReadAdvance<"ReadVCLMUL", 0>;
1096+
defm "" : LMULReadAdvance<"ReadVCLMULH", 0>;
1097+
defm "" : LMULReadAdvance<"ReadVANDN", 0>;
1098+
defm "" : LMULReadAdvance<"ReadVBREV8", 0>;
1099+
defm "" : LMULReadAdvance<"ReadVREV8", 0>;
1100+
defm "" : LMULReadAdvance<"ReadVROL", 0>;
1101+
defm "" : LMULReadAdvance<"ReadVROR", 0>;
1102+
defm "" : LMULReadAdvance<"ReadVGHSH", 0>;
1103+
defm "" : LMULReadAdvance<"ReadVGMUL", 0>;
1104+
defm "" : LMULReadAdvance<"ReadVSHA2CH", 0>;
1105+
defm "" : LMULReadAdvance<"ReadVSHA2CL", 0>;
1106+
defm "" : LMULReadAdvance<"ReadVSHA2MS", 0>;
1107+
defm "" : LMULReadAdvance<"ReadVAESMV", 0>;
1108+
defm "" : LMULReadAdvance<"ReadVAESKF1", 0>;
1109+
defm "" : LMULReadAdvance<"ReadVAESKF2", 0>;
1110+
defm "" : LMULReadAdvance<"ReadVAESZ", 0>;
1111+
defm "" : LMULReadAdvance<"ReadVSM4K", 0>;
1112+
defm "" : LMULReadAdvance<"ReadVSM4R", 0>;
1113+
defm "" : LMULReadAdvance<"ReadVSM3C", 0>;
1114+
defm "" : LMULReadAdvance<"ReadVSM3ME", 0>;
1115+
10351116
//===----------------------------------------------------------------------===//
10361117
// Unsupported extensions
10371118
defm : UnsupportedSchedZabha;

‎llvm/lib/Target/RISCV/RISCVSchedSyntacoreSCR1.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -213,4 +213,5 @@ defm : UnsupportedSchedZbkx;
213213
defm : UnsupportedSchedZfa;
214214
defm : UnsupportedSchedZfh;
215215
defm : UnsupportedSchedXsfvcp;
216+
defm : UnsupportedSchedZvk;
216217
}

‎llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td

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@@ -312,4 +312,5 @@ defm : UnsupportedSchedZfh;
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defm : UnsupportedSchedSFB;
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defm : UnsupportedSchedZabha;
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defm : UnsupportedSchedXsfvcp;
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defm : UnsupportedSchedZvk;
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}

‎llvm/lib/Target/RISCV/RISCVSchedule.td

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@@ -297,3 +297,4 @@ def : ReadAdvance<ReadAtomicHD, 0>;
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include "RISCVScheduleZb.td"
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include "RISCVScheduleV.td"
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include "RISCVScheduleXSf.td"
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include "RISCVScheduleZvk.td"

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