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Commit 91665b7

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Add tablegen patterns
1 parent bb6c35c commit 91665b7

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4 files changed

+37
-11
lines changed

4 files changed

+37
-11
lines changed

llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -98,8 +98,8 @@ def : GINodeEquiv<G_FPTOSI, fp_to_sint>;
9898
def : GINodeEquiv<G_FPTOUI, fp_to_uint>;
9999
def : GINodeEquiv<G_SITOFP, sint_to_fp>;
100100
def : GINodeEquiv<G_UITOFP, uint_to_fp>;
101-
def : GINodeEquiv<G_FPTOSI_SAT, fp_to_sint_sat>;
102-
def : GINodeEquiv<G_FPTOUI_SAT, fp_to_uint_sat>;
101+
def : GINodeEquiv<G_FPTOSI_SAT, fp_to_sint_sat_gi>;
102+
def : GINodeEquiv<G_FPTOUI_SAT, fp_to_uint_sat_gi>;
103103
def : GINodeEquiv<G_FADD, fadd>;
104104
def : GINodeEquiv<G_FSUB, fsub>;
105105
def : GINodeEquiv<G_FMA, fma>;

llvm/include/llvm/Target/TargetSelectionDAG.td

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -569,6 +569,8 @@ def fp_to_sint : SDNode<"ISD::FP_TO_SINT" , SDTFPToIntOp>;
569569
def fp_to_uint : SDNode<"ISD::FP_TO_UINT" , SDTFPToIntOp>;
570570
def fp_to_sint_sat : SDNode<"ISD::FP_TO_SINT_SAT" , SDTFPToIntSatOp>;
571571
def fp_to_uint_sat : SDNode<"ISD::FP_TO_UINT_SAT" , SDTFPToIntSatOp>;
572+
def fp_to_sint_sat_gi : SDNode<"ISD::FP_TO_SINT_SAT" , SDTFPToIntOp>;
573+
def fp_to_uint_sat_gi : SDNode<"ISD::FP_TO_UINT_SAT" , SDTFPToIntOp>;
572574
def f16_to_fp : SDNode<"ISD::FP16_TO_FP" , SDTIntToFPOp>;
573575
def fp_to_f16 : SDNode<"ISD::FP_TO_FP16" , SDTFPToIntOp>;
574576
def bf16_to_fp : SDNode<"ISD::BF16_TO_FP" , SDTIntToFPOp>;

llvm/lib/Target/AArch64/AArch64InstrInfo.td

Lines changed: 33 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4724,7 +4724,7 @@ defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", any_fp_to_sint>;
47244724
defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", any_fp_to_uint>;
47254725

47264726
// AArch64's FCVT instructions saturate when out of range.
4727-
multiclass FPToIntegerSatPats<SDNode to_int_sat, string INST> {
4727+
multiclass FPToIntegerSatPats<SDNode to_int_sat, SDNode to_int_sat_gi, string INST> {
47284728
let Predicates = [HasFullFP16] in {
47294729
def : Pat<(i32 (to_int_sat f16:$Rn, i32)),
47304730
(!cast<Instruction>(INST # UWHr) f16:$Rn)>;
@@ -4740,6 +4740,21 @@ multiclass FPToIntegerSatPats<SDNode to_int_sat, string INST> {
47404740
def : Pat<(i64 (to_int_sat f64:$Rn, i64)),
47414741
(!cast<Instruction>(INST # UXDr) f64:$Rn)>;
47424742

4743+
let Predicates = [HasFullFP16] in {
4744+
def : Pat<(i32 (to_int_sat_gi f16:$Rn)),
4745+
(!cast<Instruction>(INST # UWHr) f16:$Rn)>;
4746+
def : Pat<(i64 (to_int_sat_gi f16:$Rn)),
4747+
(!cast<Instruction>(INST # UXHr) f16:$Rn)>;
4748+
}
4749+
def : Pat<(i32 (to_int_sat_gi f32:$Rn)),
4750+
(!cast<Instruction>(INST # UWSr) f32:$Rn)>;
4751+
def : Pat<(i64 (to_int_sat_gi f32:$Rn)),
4752+
(!cast<Instruction>(INST # UXSr) f32:$Rn)>;
4753+
def : Pat<(i32 (to_int_sat_gi f64:$Rn)),
4754+
(!cast<Instruction>(INST # UWDr) f64:$Rn)>;
4755+
def : Pat<(i64 (to_int_sat_gi f64:$Rn)),
4756+
(!cast<Instruction>(INST # UXDr) f64:$Rn)>;
4757+
47434758
let Predicates = [HasFullFP16] in {
47444759
def : Pat<(i32 (to_int_sat (fmul f16:$Rn, fixedpoint_f16_i32:$scale), i32)),
47454760
(!cast<Instruction>(INST # SWHri) $Rn, $scale)>;
@@ -4754,10 +4769,25 @@ multiclass FPToIntegerSatPats<SDNode to_int_sat, string INST> {
47544769
(!cast<Instruction>(INST # SWDri) $Rn, $scale)>;
47554770
def : Pat<(i64 (to_int_sat (fmul f64:$Rn, fixedpoint_f64_i64:$scale), i64)),
47564771
(!cast<Instruction>(INST # SXDri) $Rn, $scale)>;
4772+
4773+
let Predicates = [HasFullFP16] in {
4774+
def : Pat<(i32 (to_int_sat_gi (fmul f16:$Rn, fixedpoint_f16_i32:$scale))),
4775+
(!cast<Instruction>(INST # SWHri) $Rn, $scale)>;
4776+
def : Pat<(i64 (to_int_sat_gi (fmul f16:$Rn, fixedpoint_f16_i64:$scale))),
4777+
(!cast<Instruction>(INST # SXHri) $Rn, $scale)>;
4778+
}
4779+
def : Pat<(i32 (to_int_sat_gi (fmul f32:$Rn, fixedpoint_f32_i32:$scale))),
4780+
(!cast<Instruction>(INST # SWSri) $Rn, $scale)>;
4781+
def : Pat<(i64 (to_int_sat_gi (fmul f32:$Rn, fixedpoint_f32_i64:$scale))),
4782+
(!cast<Instruction>(INST # SXSri) $Rn, $scale)>;
4783+
def : Pat<(i32 (to_int_sat_gi (fmul f64:$Rn, fixedpoint_f64_i32:$scale))),
4784+
(!cast<Instruction>(INST # SWDri) $Rn, $scale)>;
4785+
def : Pat<(i64 (to_int_sat_gi (fmul f64:$Rn, fixedpoint_f64_i64:$scale))),
4786+
(!cast<Instruction>(INST # SXDri) $Rn, $scale)>;
47574787
}
47584788

4759-
defm : FPToIntegerSatPats<fp_to_sint_sat, "FCVTZS">;
4760-
defm : FPToIntegerSatPats<fp_to_uint_sat, "FCVTZU">;
4789+
defm : FPToIntegerSatPats<fp_to_sint_sat, fp_to_sint_sat_gi, "FCVTZS">;
4790+
defm : FPToIntegerSatPats<fp_to_uint_sat, fp_to_uint_sat_gi, "FCVTZU">;
47614791

47624792
multiclass FPToIntegerIntPats<Intrinsic round, string INST> {
47634793
let Predicates = [HasFullFP16] in {

llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2152,12 +2152,6 @@ bool AArch64InstructionSelector::preISelLower(MachineInstr &I) {
21522152
}
21532153
return false;
21542154
}
2155-
case TargetOpcode::G_FPTOSI_SAT:
2156-
I.setDesc(TII.get(TargetOpcode::G_FPTOSI));
2157-
return true;
2158-
case TargetOpcode::G_FPTOUI_SAT:
2159-
I.setDesc(TII.get(TargetOpcode::G_FPTOUI));
2160-
return true;
21612155
default:
21622156
return false;
21632157
}

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