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[SDAG] Add pre-commit tests. NFC.
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‎llvm/test/CodeGen/AArch64/fpclass-test.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -mtriple=aarch64 < %s | FileCheck %s
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define i1 @test_is_inf_or_nan(double %arg) {
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; CHECK-LABEL: test_is_inf_or_nan:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fabs d0, d0
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; CHECK-NEXT: mov x8, #9218868437227405312 // =0x7ff0000000000000
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; CHECK-NEXT: fmov d1, x8
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; CHECK-NEXT: fcmp d0, d1
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; CHECK-NEXT: cset w8, eq
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; CHECK-NEXT: csinc w0, w8, wzr, vc
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; CHECK-NEXT: ret
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%abs = tail call double @llvm.fabs.f64(double %arg)
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%ret = fcmp ueq double %abs, 0x7FF0000000000000
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ret i1 %ret
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}
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define i1 @test_is_not_inf_or_nan(double %arg) {
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; CHECK-LABEL: test_is_not_inf_or_nan:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fabs d0, d0
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; CHECK-NEXT: mov x8, #9218868437227405312 // =0x7ff0000000000000
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; CHECK-NEXT: fmov d1, x8
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; CHECK-NEXT: fcmp d0, d1
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; CHECK-NEXT: cset w8, mi
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; CHECK-NEXT: csinc w0, w8, wzr, le
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; CHECK-NEXT: ret
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%abs = tail call double @llvm.fabs.f64(double %arg)
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%ret = fcmp one double %abs, 0x7FF0000000000000
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ret i1 %ret
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}
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define i1 @test_is_inf(double %arg) {
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; CHECK-LABEL: test_is_inf:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fabs d0, d0
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; CHECK-NEXT: mov x8, #9218868437227405312 // =0x7ff0000000000000
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; CHECK-NEXT: fmov d1, x8
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; CHECK-NEXT: fcmp d0, d1
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%abs = tail call double @llvm.fabs.f64(double %arg)
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%ret = fcmp oeq double %abs, 0x7FF0000000000000
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ret i1 %ret
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}
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define i1 @test_is_not_inf(double %arg) {
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; CHECK-LABEL: test_is_not_inf:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fabs d0, d0
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; CHECK-NEXT: mov x8, #9218868437227405312 // =0x7ff0000000000000
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; CHECK-NEXT: fmov d1, x8
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; CHECK-NEXT: fcmp d0, d1
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; CHECK-NEXT: cset w0, ne
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; CHECK-NEXT: ret
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%abs = tail call double @llvm.fabs.f64(double %arg)
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%ret = fcmp une double %abs, 0x7FF0000000000000
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ret i1 %ret
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}
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define i1 @test_fp128_is_inf_or_nan(fp128 %arg) {
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; CHECK-LABEL: test_fp128_is_inf_or_nan:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #64
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; CHECK-NEXT: stp x30, x19, [sp, #48] // 16-byte Folded Spill
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; CHECK-NEXT: .cfi_def_cfa_offset 64
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; CHECK-NEXT: .cfi_offset w19, -8
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; CHECK-NEXT: .cfi_offset w30, -16
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; CHECK-NEXT: str q0, [sp, #32]
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; CHECK-NEXT: ldrb w8, [sp, #47]
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; CHECK-NEXT: and w8, w8, #0x7f
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; CHECK-NEXT: strb w8, [sp, #47]
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; CHECK-NEXT: adrp x8, .LCPI4_0
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; CHECK-NEXT: ldr q0, [sp, #32]
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; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI4_0]
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; CHECK-NEXT: str q0, [sp, #16] // 16-byte Folded Spill
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; CHECK-NEXT: str q1, [sp] // 16-byte Folded Spill
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; CHECK-NEXT: bl __eqtf2
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; CHECK-NEXT: ldp q1, q0, [sp] // 32-byte Folded Reload
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; CHECK-NEXT: mov w19, w0
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; CHECK-NEXT: bl __unordtf2
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; CHECK-NEXT: cmp w0, #0
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; CHECK-NEXT: ccmp w19, #0, #4, eq
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; CHECK-NEXT: ldp x30, x19, [sp, #48] // 16-byte Folded Reload
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: add sp, sp, #64
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; CHECK-NEXT: ret
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%abs = tail call fp128 @llvm.fabs.f128(fp128 %arg)
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%ret = fcmp ueq fp128 %abs, 0xL00000000000000007FFF000000000000
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ret i1 %ret
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}
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define i1 @test_fp128_is_not_inf_or_nan(fp128 %arg) {
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; CHECK-LABEL: test_fp128_is_not_inf_or_nan:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #64
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; CHECK-NEXT: stp x30, x19, [sp, #48] // 16-byte Folded Spill
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; CHECK-NEXT: .cfi_def_cfa_offset 64
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; CHECK-NEXT: .cfi_offset w19, -8
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; CHECK-NEXT: .cfi_offset w30, -16
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; CHECK-NEXT: str q0, [sp, #32]
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; CHECK-NEXT: ldrb w8, [sp, #47]
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; CHECK-NEXT: and w8, w8, #0x7f
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; CHECK-NEXT: strb w8, [sp, #47]
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; CHECK-NEXT: adrp x8, .LCPI5_0
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; CHECK-NEXT: ldr q0, [sp, #32]
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; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI5_0]
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; CHECK-NEXT: str q0, [sp, #16] // 16-byte Folded Spill
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; CHECK-NEXT: str q1, [sp] // 16-byte Folded Spill
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; CHECK-NEXT: bl __eqtf2
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; CHECK-NEXT: ldp q1, q0, [sp] // 32-byte Folded Reload
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; CHECK-NEXT: mov w19, w0
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; CHECK-NEXT: bl __unordtf2
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; CHECK-NEXT: cmp w0, #0
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; CHECK-NEXT: ccmp w19, #0, #4, eq
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; CHECK-NEXT: ldp x30, x19, [sp, #48] // 16-byte Folded Reload
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; CHECK-NEXT: cset w0, ne
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; CHECK-NEXT: add sp, sp, #64
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; CHECK-NEXT: ret
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%abs = tail call fp128 @llvm.fabs.f128(fp128 %arg)
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%ret = fcmp one fp128 %abs, 0xL00000000000000007FFF000000000000
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ret i1 %ret
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}
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define i1 @test_fp128_is_inf(fp128 %arg) {
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; CHECK-LABEL: test_fp128_is_inf:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #32
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; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: .cfi_offset w30, -16
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; CHECK-NEXT: str q0, [sp]
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; CHECK-NEXT: ldrb w8, [sp, #15]
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; CHECK-NEXT: and w8, w8, #0x7f
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; CHECK-NEXT: strb w8, [sp, #15]
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; CHECK-NEXT: adrp x8, .LCPI6_0
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; CHECK-NEXT: ldr q0, [sp]
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; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI6_0]
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; CHECK-NEXT: bl __eqtf2
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; CHECK-NEXT: cmp w0, #0
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; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: add sp, sp, #32
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; CHECK-NEXT: ret
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%abs = tail call fp128 @llvm.fabs.f128(fp128 %arg)
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%ret = fcmp oeq fp128 %abs, 0xL00000000000000007FFF000000000000
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ret i1 %ret
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}
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define i1 @test_fp128_is_not_inf(fp128 %arg) {
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; CHECK-LABEL: test_fp128_is_not_inf:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #32
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; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: .cfi_offset w30, -16
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; CHECK-NEXT: str q0, [sp]
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; CHECK-NEXT: ldrb w8, [sp, #15]
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; CHECK-NEXT: and w8, w8, #0x7f
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; CHECK-NEXT: strb w8, [sp, #15]
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; CHECK-NEXT: adrp x8, .LCPI7_0
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; CHECK-NEXT: ldr q0, [sp]
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; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI7_0]
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; CHECK-NEXT: bl __netf2
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; CHECK-NEXT: cmp w0, #0
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; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
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; CHECK-NEXT: cset w0, ne
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; CHECK-NEXT: add sp, sp, #32
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; CHECK-NEXT: ret
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%abs = tail call fp128 @llvm.fabs.f128(fp128 %arg)
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%ret = fcmp une fp128 %abs, 0xL00000000000000007FFF000000000000
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ret i1 %ret
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}

‎llvm/test/CodeGen/RISCV/fpclass-test.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -mtriple=riscv64 -mattr=+f,+d < %s | FileCheck %s
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define i1 @test_is_inf_or_nan(double %arg) {
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; CHECK-LABEL: test_is_inf_or_nan:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fclass.d a0, fa0
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; CHECK-NEXT: andi a0, a0, 897
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; CHECK-NEXT: snez a0, a0
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; CHECK-NEXT: ret
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%abs = tail call double @llvm.fabs.f64(double %arg)
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%ret = fcmp ueq double %abs, 0x7FF0000000000000
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ret i1 %ret
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}
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define i1 @test_is_not_inf_or_nan(double %arg) {
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; CHECK-LABEL: test_is_not_inf_or_nan:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, %hi(.LCPI1_0)
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; CHECK-NEXT: fld fa5, %lo(.LCPI1_0)(a0)
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; CHECK-NEXT: fabs.d fa4, fa0
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; CHECK-NEXT: flt.d a0, fa4, fa5
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; CHECK-NEXT: ret
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%abs = tail call double @llvm.fabs.f64(double %arg)
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%ret = fcmp one double %abs, 0x7FF0000000000000
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ret i1 %ret
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}
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define i1 @test_is_inf(double %arg) {
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; CHECK-LABEL: test_is_inf:
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; CHECK: # %bb.0:
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; CHECK-NEXT: fclass.d a0, fa0
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; CHECK-NEXT: andi a0, a0, 129
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; CHECK-NEXT: snez a0, a0
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; CHECK-NEXT: ret
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%abs = tail call double @llvm.fabs.f64(double %arg)
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%ret = fcmp oeq double %abs, 0x7FF0000000000000
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ret i1 %ret
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}
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define i1 @test_is_not_inf(double %arg) {
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; CHECK-LABEL: test_is_not_inf:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, %hi(.LCPI3_0)
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; CHECK-NEXT: fld fa5, %lo(.LCPI3_0)(a0)
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; CHECK-NEXT: fabs.d fa4, fa0
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; CHECK-NEXT: feq.d a0, fa4, fa5
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; CHECK-NEXT: xori a0, a0, 1
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; CHECK-NEXT: ret
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%abs = tail call double @llvm.fabs.f64(double %arg)
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%ret = fcmp une double %abs, 0x7FF0000000000000
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ret i1 %ret
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}
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define i1 @test_fp128_is_inf_or_nan(fp128 %arg) {
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; CHECK-LABEL: test_fp128_is_inf_or_nan:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi sp, sp, -48
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
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; CHECK-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
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; CHECK-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
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; CHECK-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
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; CHECK-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
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; CHECK-NEXT: .cfi_offset ra, -8
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; CHECK-NEXT: .cfi_offset s0, -16
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; CHECK-NEXT: .cfi_offset s1, -24
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; CHECK-NEXT: .cfi_offset s2, -32
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; CHECK-NEXT: .cfi_offset s3, -40
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; CHECK-NEXT: mv s0, a0
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; CHECK-NEXT: slli a1, a1, 1
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; CHECK-NEXT: srli s1, a1, 1
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; CHECK-NEXT: lui s2, 32767
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; CHECK-NEXT: slli s2, s2, 36
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; CHECK-NEXT: mv a1, s1
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; CHECK-NEXT: li a2, 0
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; CHECK-NEXT: mv a3, s2
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; CHECK-NEXT: call __eqtf2
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; CHECK-NEXT: seqz s3, a0
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; CHECK-NEXT: mv a0, s0
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; CHECK-NEXT: mv a1, s1
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; CHECK-NEXT: li a2, 0
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; CHECK-NEXT: mv a3, s2
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; CHECK-NEXT: call __unordtf2
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; CHECK-NEXT: snez a0, a0
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; CHECK-NEXT: or a0, a0, s3
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; CHECK-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
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; CHECK-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
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; CHECK-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
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; CHECK-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
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; CHECK-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
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; CHECK-NEXT: addi sp, sp, 48
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; CHECK-NEXT: ret
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%abs = tail call fp128 @llvm.fabs.f128(fp128 %arg)
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%ret = fcmp ueq fp128 %abs, 0xL00000000000000007FFF000000000000
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ret i1 %ret
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}
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define i1 @test_fp128_is_not_inf_or_nan(fp128 %arg) {
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; CHECK-LABEL: test_fp128_is_not_inf_or_nan:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi sp, sp, -48
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; CHECK-NEXT: .cfi_def_cfa_offset 48
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; CHECK-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
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; CHECK-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
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; CHECK-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
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; CHECK-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
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; CHECK-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
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; CHECK-NEXT: .cfi_offset ra, -8
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; CHECK-NEXT: .cfi_offset s0, -16
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; CHECK-NEXT: .cfi_offset s1, -24
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; CHECK-NEXT: .cfi_offset s2, -32
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; CHECK-NEXT: .cfi_offset s3, -40
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; CHECK-NEXT: mv s0, a0
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; CHECK-NEXT: slli a1, a1, 1
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; CHECK-NEXT: srli s1, a1, 1
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; CHECK-NEXT: lui s2, 32767
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; CHECK-NEXT: slli s2, s2, 36
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; CHECK-NEXT: mv a1, s1
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; CHECK-NEXT: li a2, 0
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; CHECK-NEXT: mv a3, s2
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; CHECK-NEXT: call __eqtf2
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; CHECK-NEXT: snez s3, a0
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; CHECK-NEXT: mv a0, s0
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; CHECK-NEXT: mv a1, s1
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; CHECK-NEXT: li a2, 0
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; CHECK-NEXT: mv a3, s2
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; CHECK-NEXT: call __unordtf2
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; CHECK-NEXT: seqz a0, a0
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; CHECK-NEXT: and a0, a0, s3
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; CHECK-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
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; CHECK-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
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; CHECK-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
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; CHECK-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
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; CHECK-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
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; CHECK-NEXT: addi sp, sp, 48
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; CHECK-NEXT: ret
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%abs = tail call fp128 @llvm.fabs.f128(fp128 %arg)
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%ret = fcmp one fp128 %abs, 0xL00000000000000007FFF000000000000
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ret i1 %ret
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}
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define i1 @test_fp128_is_inf(fp128 %arg) {
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; CHECK-LABEL: test_fp128_is_inf:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi sp, sp, -16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; CHECK-NEXT: .cfi_offset ra, -8
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; CHECK-NEXT: slli a1, a1, 1
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; CHECK-NEXT: srli a1, a1, 1
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; CHECK-NEXT: lui a3, 32767
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; CHECK-NEXT: slli a3, a3, 36
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; CHECK-NEXT: li a2, 0
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; CHECK-NEXT: call __eqtf2
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; CHECK-NEXT: seqz a0, a0
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; CHECK-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; CHECK-NEXT: addi sp, sp, 16
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; CHECK-NEXT: ret
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%abs = tail call fp128 @llvm.fabs.f128(fp128 %arg)
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%ret = fcmp oeq fp128 %abs, 0xL00000000000000007FFF000000000000
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ret i1 %ret
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}
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define i1 @test_fp128_is_not_inf(fp128 %arg) {
166+
; CHECK-LABEL: test_fp128_is_not_inf:
167+
; CHECK: # %bb.0:
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; CHECK-NEXT: addi sp, sp, -16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
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; CHECK-NEXT: .cfi_offset ra, -8
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; CHECK-NEXT: slli a1, a1, 1
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; CHECK-NEXT: srli a1, a1, 1
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; CHECK-NEXT: lui a3, 32767
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; CHECK-NEXT: slli a3, a3, 36
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; CHECK-NEXT: li a2, 0
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; CHECK-NEXT: call __netf2
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; CHECK-NEXT: snez a0, a0
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; CHECK-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
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; CHECK-NEXT: addi sp, sp, 16
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; CHECK-NEXT: ret
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%abs = tail call fp128 @llvm.fabs.f128(fp128 %arg)
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%ret = fcmp une fp128 %abs, 0xL00000000000000007FFF000000000000
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ret i1 %ret
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}

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