Revert "ARM: Remove override of shouldRewriteCopySrc (#125219)"

This reverts commit 9d90f8b.

Test fails the machine verifier. There's a bug somewhere, the
unrepresentable cases should be avoided by the default logic.

Author: arsenm

llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp

@@ -961,3 +961,17 @@ bool ARMBaseRegisterInfo::shouldCoalesce(MachineInstr *MI,
   }
   return false;
 }
+
+bool ARMBaseRegisterInfo::shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
+                                               unsigned DefSubReg,
+                                               const TargetRegisterClass *SrcRC,
+                                               unsigned SrcSubReg) const {
+  // We can't extract an SPR from an arbitary DPR (as opposed to a DPR_VFP2).
+  if (DefRC == &ARM::SPRRegClass && DefSubReg == 0 &&
+      SrcRC == &ARM::DPRRegClass &&
+      (SrcSubReg == ARM::ssub_0 || SrcSubReg == ARM::ssub_1))
+    return false;
+
+  return TargetRegisterInfo::shouldRewriteCopySrc(DefRC, DefSubReg,
+                                                  SrcRC, SrcSubReg);
+}

llvm/lib/Target/ARM/ARMBaseRegisterInfo.h

@@ -159,6 +159,11 @@ class ARMBaseRegisterInfo : public ARMGenRegisterInfo {
                       const TargetRegisterClass *NewRC,
                       LiveIntervals &LIS) const override;
 
+  bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
+                            unsigned DefSubReg,
+                            const TargetRegisterClass *SrcRC,
+                            unsigned SrcSubReg) const override;
+
   int getSEHRegNum(unsigned i) const { return getEncodingValue(i); }
 };
 

llvm/test/CodeGen/ARM/shouldRewriteCopySrc.ll

@@ -12,8 +12,8 @@ define float @shouldRewriteCopySrc(double %arg) #0 {
 ; CHECK-NEXT:    @APP
 ; CHECK-NEXT:    nop
 ; CHECK-NEXT:    @NO_APP
-; CHECK-NEXT:    vmov.f64 d0, d16
-; CHECK-NEXT:    @ kill: def $s0 killed $s0 killed $d0
+; CHECK-NEXT:    vmov r0, r1, d16
+; CHECK-NEXT:    vmov s0, r0
 ; CHECK-NEXT:    vpop {d8, d9, d10, d11, d12, d13, d14, d15}
 ; CHECK-NEXT:    bx lr
 bb: