Adjust targets for G_POISON

Author: mtsokol

llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

@@ -3594,7 +3594,8 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
     return selectIntrinsic(I, MRI);
   case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
     return selectIntrinsicWithSideEffects(I, MRI);
-  case TargetOpcode::G_IMPLICIT_DEF: {
+  case TargetOpcode::G_IMPLICIT_DEF:
+  case TargetOpcode::G_POISON: {
     I.setDesc(TII.get(TargetOpcode::IMPLICIT_DEF));
     const LLT DstTy = MRI.getType(I.getOperand(0).getReg());
     const Register DstReg = I.getOperand(0).getReg();
@@ -5860,8 +5861,13 @@ bool AArch64InstructionSelector::tryOptBuildVecToSubregToReg(
   const RegisterBank &DstRB = *RBI.getRegBank(Dst, MRI, TRI);
   if (EltRB != DstRB)
     return false;
-  if (any_of(drop_begin(I.operands(), 2), [&MRI](const MachineOperand &Op) {
-        return !getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, Op.getReg(), MRI);
+  if (any_of(drop_begin(I.operands(), 2),
+             [&MRI](const MachineOperand &Op) {
+               return !getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, Op.getReg(),
+                                    MRI);
+             }) &&
+      any_of(drop_begin(I.operands(), 2), [&MRI](const MachineOperand &Op) {
+        return !getOpcodeDef(TargetOpcode::G_POISON, Op.getReg(), MRI);
       }))
     return false;
   unsigned SubReg;

llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

@@ -92,7 +92,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
   const bool HasSVE = ST.hasSVE();
 
   getActionDefinitionsBuilder(
-      {G_IMPLICIT_DEF, G_FREEZE, G_CONSTANT_FOLD_BARRIER})
+      {G_IMPLICIT_DEF, G_POISON, G_FREEZE, G_CONSTANT_FOLD_BARRIER})
       .legalFor({p0, s8, s16, s32, s64})
       .legalFor({v2s8, v4s8, v8s8, v16s8, v2s16, v4s16, v8s16, v2s32, v4s32,
                  v2s64, v2p0})

llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp

@@ -266,9 +266,10 @@ bool matchDupFromInsertVectorElt(int Lane, MachineInstr &MI,
                              MI.getOperand(1).getReg(), MRI);
   if (!InsMI)
     return false;
-  // Match the undef vector operand.
+  // Match the undef/poison vector operand.
   if (!getOpcodeDef(TargetOpcode::G_IMPLICIT_DEF, InsMI->getOperand(1).getReg(),
-                    MRI))
+                    MRI) &&
+      !getOpcodeDef(TargetOpcode::G_POISON, InsMI->getOperand(1).getReg(), MRI))
     return false;
 
   // Match the index constant 0.

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

@@ -4047,6 +4047,7 @@ bool AMDGPUInstructionSelector::select(MachineInstr &I) {
   case TargetOpcode::G_BUILD_VECTOR_TRUNC:
     return selectG_BUILD_VECTOR(I);
   case TargetOpcode::G_IMPLICIT_DEF:
+  case TargetOpcode::G_POISON:
     return selectG_IMPLICIT_DEF(I);
   case TargetOpcode::G_INSERT:
     return selectG_INSERT(I);

llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp

@@ -477,7 +477,8 @@ AMDGPURegisterBankInfo::getInstrAlternativeMappings(
   InstructionMappings AltMappings;
   switch (MI.getOpcode()) {
   case TargetOpcode::G_CONSTANT:
-  case TargetOpcode::G_IMPLICIT_DEF: {
+  case TargetOpcode::G_IMPLICIT_DEF:
+  case TargetOpcode::G_POISON: {
     unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
     if (Size == 1) {
       static const OpRegBankEntry<1> Table[3] = {

llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp

@@ -812,6 +812,7 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
     return true;
   }
   case TargetOpcode::G_IMPLICIT_DEF:
+  case TargetOpcode::G_POISON:
     return selectImplicitDef(MI, MIB);
   case TargetOpcode::G_UNMERGE_VALUES:
     return selectUnmergeValues(MI, MIB);
@@ -1030,7 +1031,8 @@ bool RISCVInstructionSelector::selectCopy(MachineInstr &MI) const {
 
 bool RISCVInstructionSelector::selectImplicitDef(MachineInstr &MI,
                                                  MachineIRBuilder &MIB) const {
-  assert(MI.getOpcode() == TargetOpcode::G_IMPLICIT_DEF);
+  assert(MI.getOpcode() == TargetOpcode::G_IMPLICIT_DEF ||
+         MI.getOpcode() == TargetOpcode::G_POISON);
 
   const Register DstReg = MI.getOperand(0).getReg();
   const TargetRegisterClass *DstRC = getRegClassForTypeOnBank(

llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

@@ -255,7 +255,7 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
   // TODO: transform illegal vector types into legal vector type
   // TODO: Merge with G_FREEZE?
   getActionDefinitionsBuilder(
-      {G_IMPLICIT_DEF, G_CONSTANT_FOLD_BARRIER})
+      {G_IMPLICIT_DEF, G_POISON, G_CONSTANT_FOLD_BARRIER})
       .legalFor({s32, sXLen, p0})
       .legalIf(typeIsLegalBoolVec(0, BoolVecTys, ST))
       .legalIf(typeIsLegalIntOrFPVec(0, IntOrFPVecTys, ST))
@@ -1172,7 +1172,8 @@ bool RISCVLegalizerInfo::legalizeInsertSubvector(MachineInstr &MI,
   LLT LitTy = MRI.getType(LitVec);
 
   if (Idx == 0 ||
-      MRI.getVRegDef(BigVec)->getOpcode() == TargetOpcode::G_IMPLICIT_DEF)
+      MRI.getVRegDef(BigVec)->getOpcode() == TargetOpcode::G_IMPLICIT_DEF ||
+      MRI.getVRegDef(BigVec)->getOpcode() == TargetOpcode::G_POISON)
     return true;
 
   // We don't have the ability to slide mask vectors up indexed by their i1

llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp

@@ -288,7 +288,8 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   case TargetOpcode::G_ZEXTLOAD:
     return getInstructionMapping(DefaultMappingID, /*Cost=*/1, GPRValueMapping,
                                  NumOperands);
-  case TargetOpcode::G_IMPLICIT_DEF: {
+  case TargetOpcode::G_IMPLICIT_DEF:
+  case TargetOpcode::G_POSION: {
     Register Dst = MI.getOperand(0).getReg();
     LLT DstTy = MRI.getType(Dst);
     unsigned DstMinSize = DstTy.getSizeInBits().getKnownMinValue();

llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp

@@ -548,7 +548,8 @@ bool SPIRVInstructionSelector::select(MachineInstr &I) {
   Register ResVReg = HasDefs ? I.getOperand(0).getReg() : Register(0);
   SPIRVType *ResType = HasDefs ? GR.getSPIRVTypeForVReg(ResVReg) : nullptr;
   assert(!HasDefs || ResType || I.getOpcode() == TargetOpcode::G_GLOBAL_VALUE ||
-         I.getOpcode() == TargetOpcode::G_IMPLICIT_DEF);
+         I.getOpcode() == TargetOpcode::G_IMPLICIT_DEF ||
+         I.getOpcode() == TargetOpcode::G_POISON);
   if (spvSelect(ResVReg, ResType, I)) {
     if (HasDefs) // Make all vregs 64 bits (for SPIR-V IDs).
       for (unsigned i = 0; i < I.getNumDefs(); ++i)
@@ -598,6 +599,7 @@ bool SPIRVInstructionSelector::spvSelect(Register ResVReg,
   case TargetOpcode::G_GLOBAL_VALUE:
     return selectGlobalValue(ResVReg, I);
   case TargetOpcode::G_IMPLICIT_DEF:
+  case TargetOpcode::G_POISON:
     return selectOpUndef(ResVReg, ResType, I);
   case TargetOpcode::G_FREEZE:
     return selectFreeze(ResVReg, ResType, I);
@@ -2326,7 +2328,8 @@ bool SPIRVInstructionSelector::selectFreeze(Register ResVReg,
     case SPIRV::ASSIGN_TYPE:
       if (MachineInstr *AssignToDef =
               MRI->getVRegDef(Def->getOperand(1).getReg())) {
-        if (AssignToDef->getOpcode() == TargetOpcode::G_IMPLICIT_DEF)
+        if (AssignToDef->getOpcode() == TargetOpcode::G_IMPLICIT_DEF ||
+            AssignToDef->getOpcode() == TargetOpcode::G_POISON)
           Reg = Def->getOperand(2).getReg();
       }
       break;

llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp

@@ -222,7 +222,8 @@ SPIRVLegalizerInfo::SPIRVLegalizerInfo(const SPIRVSubtarget &ST) {
       all(typeInSet(0, allPtrsScalarsAndVectors),
           typeInSet(1, allPtrsScalarsAndVectors)));
 
-  getActionDefinitionsBuilder({G_IMPLICIT_DEF, G_FREEZE}).alwaysLegal();
+  getActionDefinitionsBuilder({G_IMPLICIT_DEF, G_POISON, G_FREEZE})
+      .alwaysLegal();
 
   getActionDefinitionsBuilder({G_STACKSAVE, G_STACKRESTORE}).alwaysLegal();
 

llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp

@@ -93,7 +93,8 @@ addConstantsToTrack(MachineFunction &MF, SPIRVGlobalRegistry *GR,
             if (SrcMI)
               GR->add(Const, SrcMI);
             if (SrcMI && (SrcMI->getOpcode() == TargetOpcode::G_CONSTANT ||
-                          SrcMI->getOpcode() == TargetOpcode::G_IMPLICIT_DEF))
+                          SrcMI->getOpcode() == TargetOpcode::G_IMPLICIT_DEF ||
+                          SrcMI->getOpcode() == TargetOpcode::G_POISON))
               TargetExtConstTypes[SrcMI] = Const->getType();
             if (Const->isNullValue()) {
               MachineBasicBlock &DepMBB = MF.front();

llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp

@@ -113,7 +113,8 @@ class X86InstructionSelector : public InstructionSelector {
                           const TargetRegisterClass *SrcRC) const;
   bool materializeFP(MachineInstr &I, MachineRegisterInfo &MRI,
                      MachineFunction &MF) const;
-  bool selectImplicitDefOrPHI(MachineInstr &I, MachineRegisterInfo &MRI) const;
+  bool selectImplicitDefOrPoisonOrPHI(MachineInstr &I,
+                                      MachineRegisterInfo &MRI) const;
   bool selectMulDivRem(MachineInstr &I, MachineRegisterInfo &MRI,
                        MachineFunction &MF) const;
   bool selectSelect(MachineInstr &I, MachineRegisterInfo &MRI,
@@ -428,8 +429,9 @@ bool X86InstructionSelector::select(MachineInstr &I) {
   case TargetOpcode::G_BRCOND:
     return selectCondBranch(I, MRI, MF);
   case TargetOpcode::G_IMPLICIT_DEF:
+  case TargetOpcode::G_POISON:
   case TargetOpcode::G_PHI:
-    return selectImplicitDefOrPHI(I, MRI);
+    return selectImplicitDefOrPoisonOrPHI(I, MRI);
   case TargetOpcode::G_MUL:
   case TargetOpcode::G_SMULH:
   case TargetOpcode::G_UMULH:
@@ -1585,9 +1587,10 @@ bool X86InstructionSelector::materializeFP(MachineInstr &I,
   return true;
 }
 
-bool X86InstructionSelector::selectImplicitDefOrPHI(
+bool X86InstructionSelector::selectImplicitDefOrPoisonOrPHI(
     MachineInstr &I, MachineRegisterInfo &MRI) const {
   assert((I.getOpcode() == TargetOpcode::G_IMPLICIT_DEF ||
+          I.getOpcode() == TargetOpcode::G_POISON ||
           I.getOpcode() == TargetOpcode::G_PHI) &&
          "unexpected instruction");
 
@@ -1604,7 +1607,8 @@ bool X86InstructionSelector::selectImplicitDefOrPHI(
     }
   }
 
-  if (I.getOpcode() == TargetOpcode::G_IMPLICIT_DEF)
+  if (I.getOpcode() == TargetOpcode::G_IMPLICIT_DEF ||
+      I.getOpcode() == TargetOpcode::G_POISON)
     I.setDesc(TII.get(X86::IMPLICIT_DEF));
   else
     I.setDesc(TII.get(X86::PHI));

llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp

@@ -82,7 +82,7 @@ X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI,
   // todo: AVX512 bool vector predicate types
 
   // implicit/constants
-  getActionDefinitionsBuilder(G_IMPLICIT_DEF)
+  getActionDefinitionsBuilder({G_IMPLICIT_DEF, G_POISON})
       .legalIf([=](const LegalityQuery &Query) -> bool {
         // 32/64-bits needs support for s64/s128 to handle cases:
         // s64 = EXTEND (G_IMPLICIT_DEF s32) -> s64 = G_IMPLICIT_DEF

llvm/lib/Target/X86/GISel/X86RegisterBankInfo.cpp

@@ -404,6 +404,7 @@ X86RegisterBankInfo::getInstrAlternativeMappings(const MachineInstr &MI) const {
   switch (MI.getOpcode()) {
   case TargetOpcode::G_LOAD:
   case TargetOpcode::G_STORE:
+  case TargetOpcode::G_POISON:
   case TargetOpcode::G_IMPLICIT_DEF: {
     // we going to try to map 32/64/80 bit to PMI_FP32/PMI_FP64/PMI_FP80
     unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);