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paulwalker-armpaulwalker-arm
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[LLVM][InstCombine] Enable constant folding for SVE add,and,eor,fadd,fdiv,fsub,orr & sub intrinsics. (#136849)
This is the subset of binops (mul and fmul are already enabled) whose behaviour fully aligns with the equivalent SVE intrinsic. The omissions are integer divides and shifts that are defined to return poison for values where the intrinsics have a defined result. These will be covered in a seperate PR.
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-32
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2 files changed

+56
-32
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‎llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp

Lines changed: 40 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1268,9 +1268,11 @@ static SVEIntrinsicInfo constructSVEIntrinsicInfo(IntrinsicInst &II) {
12681268
case Intrinsic::aarch64_sve_fabd:
12691269
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_fabd_u);
12701270
case Intrinsic::aarch64_sve_fadd:
1271-
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_fadd_u);
1271+
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_fadd_u)
1272+
.setMatchingIROpcode(Instruction::FAdd);
12721273
case Intrinsic::aarch64_sve_fdiv:
1273-
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_fdiv_u);
1274+
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_fdiv_u)
1275+
.setMatchingIROpcode(Instruction::FDiv);
12741276
case Intrinsic::aarch64_sve_fmax:
12751277
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_fmax_u);
12761278
case Intrinsic::aarch64_sve_fmaxnm:
@@ -1293,9 +1295,11 @@ static SVEIntrinsicInfo constructSVEIntrinsicInfo(IntrinsicInst &II) {
12931295
case Intrinsic::aarch64_sve_fnmls:
12941296
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_fnmls_u);
12951297
case Intrinsic::aarch64_sve_fsub:
1296-
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_fsub_u);
1298+
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_fsub_u)
1299+
.setMatchingIROpcode(Instruction::FSub);
12971300
case Intrinsic::aarch64_sve_add:
1298-
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_add_u);
1301+
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_add_u)
1302+
.setMatchingIROpcode(Instruction::Add);
12991303
case Intrinsic::aarch64_sve_mla:
13001304
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_mla_u);
13011305
case Intrinsic::aarch64_sve_mls:
@@ -1312,7 +1316,8 @@ static SVEIntrinsicInfo constructSVEIntrinsicInfo(IntrinsicInst &II) {
13121316
case Intrinsic::aarch64_sve_smulh:
13131317
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_smulh_u);
13141318
case Intrinsic::aarch64_sve_sub:
1315-
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_sub_u);
1319+
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_sub_u)
1320+
.setMatchingIROpcode(Instruction::Sub);
13161321
case Intrinsic::aarch64_sve_uabd:
13171322
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_uabd_u);
13181323
case Intrinsic::aarch64_sve_umax:
@@ -1328,24 +1333,51 @@ static SVEIntrinsicInfo constructSVEIntrinsicInfo(IntrinsicInst &II) {
13281333
case Intrinsic::aarch64_sve_lsr:
13291334
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_lsr_u);
13301335
case Intrinsic::aarch64_sve_and:
1331-
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_and_u);
1336+
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_and_u)
1337+
.setMatchingIROpcode(Instruction::And);
13321338
case Intrinsic::aarch64_sve_bic:
13331339
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_bic_u);
13341340
case Intrinsic::aarch64_sve_eor:
1335-
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_eor_u);
1341+
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_eor_u)
1342+
.setMatchingIROpcode(Instruction::Xor);
13361343
case Intrinsic::aarch64_sve_orr:
1337-
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_orr_u);
1344+
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_orr_u)
1345+
.setMatchingIROpcode(Instruction::Or);
13381346
case Intrinsic::aarch64_sve_sqsub:
13391347
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_sqsub_u);
13401348
case Intrinsic::aarch64_sve_uqsub:
13411349
return SVEIntrinsicInfo::defaultMergingOp(Intrinsic::aarch64_sve_uqsub_u);
13421350

1351+
case Intrinsic::aarch64_sve_add_u:
1352+
return SVEIntrinsicInfo::defaultUndefOp().setMatchingIROpcode(
1353+
Instruction::Add);
1354+
case Intrinsic::aarch64_sve_and_u:
1355+
return SVEIntrinsicInfo::defaultUndefOp().setMatchingIROpcode(
1356+
Instruction::And);
1357+
case Intrinsic::aarch64_sve_eor_u:
1358+
return SVEIntrinsicInfo::defaultUndefOp().setMatchingIROpcode(
1359+
Instruction::Xor);
1360+
case Intrinsic::aarch64_sve_fadd_u:
1361+
return SVEIntrinsicInfo::defaultUndefOp().setMatchingIROpcode(
1362+
Instruction::FAdd);
1363+
case Intrinsic::aarch64_sve_fdiv_u:
1364+
return SVEIntrinsicInfo::defaultUndefOp().setMatchingIROpcode(
1365+
Instruction::FDiv);
13431366
case Intrinsic::aarch64_sve_fmul_u:
13441367
return SVEIntrinsicInfo::defaultUndefOp().setMatchingIROpcode(
13451368
Instruction::FMul);
1369+
case Intrinsic::aarch64_sve_fsub_u:
1370+
return SVEIntrinsicInfo::defaultUndefOp().setMatchingIROpcode(
1371+
Instruction::FSub);
13461372
case Intrinsic::aarch64_sve_mul_u:
13471373
return SVEIntrinsicInfo::defaultUndefOp().setMatchingIROpcode(
13481374
Instruction::Mul);
1375+
case Intrinsic::aarch64_sve_orr_u:
1376+
return SVEIntrinsicInfo::defaultUndefOp().setMatchingIROpcode(
1377+
Instruction::Or);
1378+
case Intrinsic::aarch64_sve_sub_u:
1379+
return SVEIntrinsicInfo::defaultUndefOp().setMatchingIROpcode(
1380+
Instruction::Sub);
13491381

13501382
case Intrinsic::aarch64_sve_addqv:
13511383
case Intrinsic::aarch64_sve_and_z:

‎llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-simplify-binop.ll

Lines changed: 16 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -110,7 +110,7 @@ define <vscale x 4 x i32> @constant_mul_u_after_striping_inactive_lanes(<vscale
110110
define <vscale x 4 x i32> @constant_add(<vscale x 4 x i1> %pg) #0 {
111111
; CHECK-LABEL: define <vscale x 4 x i32> @constant_add(
112112
; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
113-
; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.add.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 3))
113+
; CHECK-NEXT: [[R:%.*]] = select <vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 10), <vscale x 4 x i32> splat (i32 7)
114114
; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]
115115
;
116116
%r = call <vscale x 4 x i32> @llvm.aarch64.sve.add.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 3))
@@ -120,8 +120,7 @@ define <vscale x 4 x i32> @constant_add(<vscale x 4 x i1> %pg) #0 {
120120
define <vscale x 4 x i32> @constant_add_u(<vscale x 4 x i1> %pg) #0 {
121121
; CHECK-LABEL: define <vscale x 4 x i32> @constant_add_u(
122122
; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
123-
; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.add.u.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 3))
124-
; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]
123+
; CHECK-NEXT: ret <vscale x 4 x i32> splat (i32 10)
125124
;
126125
%r = call <vscale x 4 x i32> @llvm.aarch64.sve.add.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 3))
127126
ret <vscale x 4 x i32> %r
@@ -130,7 +129,7 @@ define <vscale x 4 x i32> @constant_add_u(<vscale x 4 x i1> %pg) #0 {
130129
define <vscale x 4 x i32> @constant_and(<vscale x 4 x i1> %pg) #0 {
131130
; CHECK-LABEL: define <vscale x 4 x i32> @constant_and(
132131
; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
133-
; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.and.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 14))
132+
; CHECK-NEXT: [[R:%.*]] = select <vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 6), <vscale x 4 x i32> splat (i32 7)
134133
; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]
135134
;
136135
%r = call <vscale x 4 x i32> @llvm.aarch64.sve.and.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 14))
@@ -140,8 +139,7 @@ define <vscale x 4 x i32> @constant_and(<vscale x 4 x i1> %pg) #0 {
140139
define <vscale x 4 x i32> @constant_and_u(<vscale x 4 x i1> %pg) #0 {
141140
; CHECK-LABEL: define <vscale x 4 x i32> @constant_and_u(
142141
; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
143-
; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.and.u.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 14))
144-
; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]
142+
; CHECK-NEXT: ret <vscale x 4 x i32> splat (i32 6)
145143
;
146144
%r = call <vscale x 4 x i32> @llvm.aarch64.sve.and.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 14))
147145
ret <vscale x 4 x i32> %r
@@ -150,7 +148,7 @@ define <vscale x 4 x i32> @constant_and_u(<vscale x 4 x i1> %pg) #0 {
150148
define <vscale x 4 x i32> @constant_eor(<vscale x 4 x i1> %pg) #0 {
151149
; CHECK-LABEL: define <vscale x 4 x i32> @constant_eor(
152150
; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
153-
; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.eor.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 3))
151+
; CHECK-NEXT: [[R:%.*]] = select <vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 4), <vscale x 4 x i32> splat (i32 7)
154152
; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]
155153
;
156154
%r = call <vscale x 4 x i32> @llvm.aarch64.sve.eor.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 3))
@@ -160,8 +158,7 @@ define <vscale x 4 x i32> @constant_eor(<vscale x 4 x i1> %pg) #0 {
160158
define <vscale x 4 x i32> @constant_eor_u(<vscale x 4 x i1> %pg) #0 {
161159
; CHECK-LABEL: define <vscale x 4 x i32> @constant_eor_u(
162160
; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
163-
; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.eor.u.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 3))
164-
; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]
161+
; CHECK-NEXT: ret <vscale x 4 x i32> splat (i32 4)
165162
;
166163
%r = call <vscale x 4 x i32> @llvm.aarch64.sve.eor.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 3))
167164
ret <vscale x 4 x i32> %r
@@ -170,7 +167,7 @@ define <vscale x 4 x i32> @constant_eor_u(<vscale x 4 x i1> %pg) #0 {
170167
define <vscale x 4 x float> @constant_fadd(<vscale x 4 x i1> %pg) #0 {
171168
; CHECK-LABEL: define <vscale x 4 x float> @constant_fadd(
172169
; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
173-
; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fadd.nxv4f32(<vscale x 4 x i1> [[PG]], <vscale x 4 x float> splat (float 7.000000e+00), <vscale x 4 x float> splat (float 6.000000e+00))
170+
; CHECK-NEXT: [[R:%.*]] = select <vscale x 4 x i1> [[PG]], <vscale x 4 x float> splat (float 1.300000e+01), <vscale x 4 x float> splat (float 7.000000e+00)
174171
; CHECK-NEXT: ret <vscale x 4 x float> [[R]]
175172
;
176173
%r = call <vscale x 4 x float> @llvm.aarch64.sve.fadd.nxv4f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> splat (float 7.0), <vscale x 4 x float> splat (float 6.0))
@@ -180,8 +177,7 @@ define <vscale x 4 x float> @constant_fadd(<vscale x 4 x i1> %pg) #0 {
180177
define <vscale x 4 x float> @constant_fadd_u(<vscale x 4 x i1> %pg) #0 {
181178
; CHECK-LABEL: define <vscale x 4 x float> @constant_fadd_u(
182179
; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
183-
; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fadd.u.nxv4f32(<vscale x 4 x i1> [[PG]], <vscale x 4 x float> splat (float 7.000000e+00), <vscale x 4 x float> splat (float 6.000000e+00))
184-
; CHECK-NEXT: ret <vscale x 4 x float> [[R]]
180+
; CHECK-NEXT: ret <vscale x 4 x float> splat (float 1.300000e+01)
185181
;
186182
%r = call <vscale x 4 x float> @llvm.aarch64.sve.fadd.u.nxv4f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> splat (float 7.0), <vscale x 4 x float> splat (float 6.0))
187183
ret <vscale x 4 x float> %r
@@ -190,7 +186,7 @@ define <vscale x 4 x float> @constant_fadd_u(<vscale x 4 x i1> %pg) #0 {
190186
define <vscale x 4 x float> @constant_fdiv(<vscale x 4 x i1> %pg) #0 {
191187
; CHECK-LABEL: define <vscale x 4 x float> @constant_fdiv(
192188
; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
193-
; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fdiv.nxv4f32(<vscale x 4 x i1> [[PG]], <vscale x 4 x float> splat (float 1.200000e+01), <vscale x 4 x float> splat (float 6.000000e+00))
189+
; CHECK-NEXT: [[R:%.*]] = select <vscale x 4 x i1> [[PG]], <vscale x 4 x float> splat (float 2.000000e+00), <vscale x 4 x float> splat (float 1.200000e+01)
194190
; CHECK-NEXT: ret <vscale x 4 x float> [[R]]
195191
;
196192
%r = call <vscale x 4 x float> @llvm.aarch64.sve.fdiv.nxv4f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> splat (float 12.0), <vscale x 4 x float> splat (float 6.0))
@@ -200,8 +196,7 @@ define <vscale x 4 x float> @constant_fdiv(<vscale x 4 x i1> %pg) #0 {
200196
define <vscale x 4 x float> @constant_fdiv_u(<vscale x 4 x i1> %pg) #0 {
201197
; CHECK-LABEL: define <vscale x 4 x float> @constant_fdiv_u(
202198
; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
203-
; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fdiv.u.nxv4f32(<vscale x 4 x i1> [[PG]], <vscale x 4 x float> splat (float 7.000000e+00), <vscale x 4 x float> splat (float 6.000000e+00))
204-
; CHECK-NEXT: ret <vscale x 4 x float> [[R]]
199+
; CHECK-NEXT: ret <vscale x 4 x float> splat (float 0x3FF2AAAAA0000000)
205200
;
206201
%r = call <vscale x 4 x float> @llvm.aarch64.sve.fdiv.u.nxv4f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> splat (float 7.0), <vscale x 4 x float> splat (float 6.0))
207202
ret <vscale x 4 x float> %r
@@ -229,7 +224,7 @@ define <vscale x 4 x float> @constant_fmul_u(<vscale x 4 x i1> %pg) #0 {
229224
define <vscale x 4 x float> @constant_fsub(<vscale x 4 x i1> %pg) #0 {
230225
; CHECK-LABEL: define <vscale x 4 x float> @constant_fsub(
231226
; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
232-
; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fsub.nxv4f32(<vscale x 4 x i1> [[PG]], <vscale x 4 x float> splat (float 7.000000e+00), <vscale x 4 x float> splat (float 6.000000e+00))
227+
; CHECK-NEXT: [[R:%.*]] = select <vscale x 4 x i1> [[PG]], <vscale x 4 x float> splat (float 1.000000e+00), <vscale x 4 x float> splat (float 7.000000e+00)
233228
; CHECK-NEXT: ret <vscale x 4 x float> [[R]]
234229
;
235230
%r = call <vscale x 4 x float> @llvm.aarch64.sve.fsub.nxv4f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> splat (float 7.0), <vscale x 4 x float> splat (float 6.0))
@@ -239,8 +234,7 @@ define <vscale x 4 x float> @constant_fsub(<vscale x 4 x i1> %pg) #0 {
239234
define <vscale x 4 x float> @constant_fsub_u(<vscale x 4 x i1> %pg) #0 {
240235
; CHECK-LABEL: define <vscale x 4 x float> @constant_fsub_u(
241236
; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
242-
; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fsub.u.nxv4f32(<vscale x 4 x i1> [[PG]], <vscale x 4 x float> splat (float 7.000000e+00), <vscale x 4 x float> splat (float 6.000000e+00))
243-
; CHECK-NEXT: ret <vscale x 4 x float> [[R]]
237+
; CHECK-NEXT: ret <vscale x 4 x float> splat (float 1.000000e+00)
244238
;
245239
%r = call <vscale x 4 x float> @llvm.aarch64.sve.fsub.u.nxv4f32(<vscale x 4 x i1> %pg, <vscale x 4 x float> splat (float 7.0), <vscale x 4 x float> splat (float 6.0))
246240
ret <vscale x 4 x float> %r
@@ -268,7 +262,7 @@ define <vscale x 4 x i32> @constant_mul_u(<vscale x 4 x i1> %pg) #0 {
268262
define <vscale x 4 x i32> @constant_orr(<vscale x 4 x i1> %pg) #0 {
269263
; CHECK-LABEL: define <vscale x 4 x i32> @constant_orr(
270264
; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
271-
; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 13), <vscale x 4 x i32> splat (i32 3))
265+
; CHECK-NEXT: [[R:%.*]] = select <vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 15), <vscale x 4 x i32> splat (i32 13)
272266
; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]
273267
;
274268
%r = call <vscale x 4 x i32> @llvm.aarch64.sve.orr.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 13), <vscale x 4 x i32> splat (i32 3))
@@ -278,8 +272,7 @@ define <vscale x 4 x i32> @constant_orr(<vscale x 4 x i1> %pg) #0 {
278272
define <vscale x 4 x i32> @constant_orr_u(<vscale x 4 x i1> %pg) #0 {
279273
; CHECK-LABEL: define <vscale x 4 x i32> @constant_orr_u(
280274
; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
281-
; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.orr.u.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 13), <vscale x 4 x i32> splat (i32 3))
282-
; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]
275+
; CHECK-NEXT: ret <vscale x 4 x i32> splat (i32 15)
283276
;
284277
%r = call <vscale x 4 x i32> @llvm.aarch64.sve.orr.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 13), <vscale x 4 x i32> splat (i32 3))
285278
ret <vscale x 4 x i32> %r
@@ -351,7 +344,7 @@ define <vscale x 4 x i32> @constant_sdiv_u_with_overflow(<vscale x 4 x i1> %pg)
351344
define <vscale x 4 x i32> @constant_sub(<vscale x 4 x i1> %pg) #0 {
352345
; CHECK-LABEL: define <vscale x 4 x i32> @constant_sub(
353346
; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
354-
; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sub.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 3))
347+
; CHECK-NEXT: [[R:%.*]] = select <vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 4), <vscale x 4 x i32> splat (i32 7)
355348
; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]
356349
;
357350
%r = call <vscale x 4 x i32> @llvm.aarch64.sve.sub.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 3))
@@ -361,8 +354,7 @@ define <vscale x 4 x i32> @constant_sub(<vscale x 4 x i1> %pg) #0 {
361354
define <vscale x 4 x i32> @constant_sub_u(<vscale x 4 x i1> %pg) #0 {
362355
; CHECK-LABEL: define <vscale x 4 x i32> @constant_sub_u(
363356
; CHECK-SAME: <vscale x 4 x i1> [[PG:%.*]]) #[[ATTR0]] {
364-
; CHECK-NEXT: [[R:%.*]] = call <vscale x 4 x i32> @llvm.aarch64.sve.sub.u.nxv4i32(<vscale x 4 x i1> [[PG]], <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 3))
365-
; CHECK-NEXT: ret <vscale x 4 x i32> [[R]]
357+
; CHECK-NEXT: ret <vscale x 4 x i32> splat (i32 4)
366358
;
367359
%r = call <vscale x 4 x i32> @llvm.aarch64.sve.sub.u.nxv4i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> splat (i32 7), <vscale x 4 x i32> splat (i32 3))
368360
ret <vscale x 4 x i32> %r

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