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[MC] Return MCRegister from MCRegisterClass::getRegister. NFC (#132126)
Replace unsigned with MCRegister at some of the call sites.
1 parent 6cd62ad commit 97213b3

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7 files changed

+38
-37
lines changed

7 files changed

+38
-37
lines changed

‎llvm/include/llvm/MC/MCRegisterInfo.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -63,7 +63,7 @@ class MCRegisterClass {
6363

6464
/// getRegister - Return the specified register in the class.
6565
///
66-
unsigned getRegister(unsigned i) const {
66+
MCRegister getRegister(unsigned i) const {
6767
assert(i < getNumRegs() && "Register number out of range!");
6868
return RegsBegin[i];
6969
}

‎llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1141,7 +1141,7 @@ bool AArch64AsmPrinter::printAsmRegInClass(const MachineOperand &MO,
11411141
assert(MO.isReg() && "Should only get here with a register!");
11421142
const TargetRegisterInfo *RI = STI->getRegisterInfo();
11431143
Register Reg = MO.getReg();
1144-
unsigned RegToPrint = RC->getRegister(RI->getEncodingValue(Reg));
1144+
MCRegister RegToPrint = RC->getRegister(RI->getEncodingValue(Reg));
11451145
if (!RI->regsOverlap(RegToPrint, Reg))
11461146
return true;
11471147
O << AArch64InstPrinter::getRegisterName(RegToPrint, AltName);

‎llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1794,8 +1794,8 @@ class AArch64Operand : public MCParsedAsmOperand {
17941794
AArch64MCRegisterClasses[AArch64::GPR64RegClassID].contains(getReg()));
17951795

17961796
const MCRegisterInfo *RI = Ctx.getRegisterInfo();
1797-
uint32_t Reg = RI->getRegClass(AArch64::GPR32RegClassID).getRegister(
1798-
RI->getEncodingValue(getReg()));
1797+
MCRegister Reg = RI->getRegClass(AArch64::GPR32RegClassID)
1798+
.getRegister(RI->getEncodingValue(getReg()));
17991799

18001800
Inst.addOperand(MCOperand::createReg(Reg));
18011801
}
@@ -1806,8 +1806,8 @@ class AArch64Operand : public MCParsedAsmOperand {
18061806
AArch64MCRegisterClasses[AArch64::GPR32RegClassID].contains(getReg()));
18071807

18081808
const MCRegisterInfo *RI = Ctx.getRegisterInfo();
1809-
uint32_t Reg = RI->getRegClass(AArch64::GPR64RegClassID).getRegister(
1810-
RI->getEncodingValue(getReg()));
1809+
MCRegister Reg = RI->getRegClass(AArch64::GPR64RegClassID)
1810+
.getRegister(RI->getEncodingValue(getReg()));
18111811

18121812
Inst.addOperand(MCOperand::createReg(Reg));
18131813
}
@@ -2227,8 +2227,8 @@ class AArch64Operand : public MCParsedAsmOperand {
22272227
return;
22282228

22292229
const MCRegisterInfo *RI = Ctx.getRegisterInfo();
2230-
uint32_t Reg = RI->getRegClass(AArch64::GPR64RegClassID)
2231-
.getRegister(RI->getEncodingValue(getReg()));
2230+
MCRegister Reg = RI->getRegClass(AArch64::GPR64RegClassID)
2231+
.getRegister(RI->getEncodingValue(getReg()));
22322232
if (Reg != AArch64::XZR)
22332233
llvm_unreachable("wrong register");
22342234

‎llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -341,7 +341,7 @@ static DecodeStatus DecodeSimpleRegisterClass(MCInst &Inst, unsigned RegNo,
341341
if (RegNo > NumRegsInClass - 1)
342342
return Fail;
343343

344-
unsigned Register =
344+
MCRegister Register =
345345
AArch64MCRegisterClasses[RegClassID].getRegister(RegNo + FirstReg);
346346
Inst.addOperand(MCOperand::createReg(Register));
347347
return Success;
@@ -355,7 +355,7 @@ DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
355355
if (RegNo & 1)
356356
return Fail;
357357

358-
unsigned Register =
358+
MCRegister Register =
359359
AArch64MCRegisterClasses[AArch64::GPR64x8ClassRegClassID].getRegister(
360360
RegNo >> 1);
361361
Inst.addOperand(MCOperand::createReg(Register));
@@ -369,7 +369,7 @@ static DecodeStatus DecodeZPRMul2_MinMax(MCInst &Inst, unsigned RegNo,
369369
unsigned Reg = (RegNo * 2) + Min;
370370
if (Reg < Min || Reg > Max || (Reg & 1))
371371
return Fail;
372-
unsigned Register =
372+
MCRegister Register =
373373
AArch64MCRegisterClasses[AArch64::ZPRRegClassID].getRegister(Reg);
374374
Inst.addOperand(MCOperand::createReg(Register));
375375
return Success;
@@ -383,7 +383,7 @@ static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
383383
if (Reg < Min || Reg > Max || (Reg & 1))
384384
return Fail;
385385

386-
unsigned Register =
386+
MCRegister Register =
387387
AArch64MCRegisterClasses[AArch64::ZPR2RegClassID].getRegister(Reg);
388388
Inst.addOperand(MCOperand::createReg(Register));
389389
return Success;
@@ -394,7 +394,7 @@ static DecodeStatus DecodeZK(MCInst &Inst, unsigned RegNo, uint64_t Address,
394394
if (RegNo > 7)
395395
return Fail;
396396

397-
unsigned Register =
397+
MCRegister Register =
398398
AArch64MCRegisterClasses[AArch64::ZPR_KRegClassID].getRegister(RegNo);
399399
Inst.addOperand(MCOperand::createReg(Register));
400400
return Success;
@@ -405,7 +405,7 @@ static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo,
405405
const void *Decoder) {
406406
if (RegNo * 4 > 28)
407407
return Fail;
408-
unsigned Register =
408+
MCRegister Register =
409409
AArch64MCRegisterClasses[AArch64::ZPR4RegClassID].getRegister(RegNo * 4);
410410
Inst.addOperand(MCOperand::createReg(Register));
411411
return Success;
@@ -449,7 +449,7 @@ static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
449449
const void *Decoder) {
450450
if ((RegNo * 2) > 14)
451451
return Fail;
452-
unsigned Register =
452+
MCRegister Register =
453453
AArch64MCRegisterClasses[AArch64::PPR2RegClassID].getRegister(RegNo * 2);
454454
Inst.addOperand(MCOperand::createReg(Register));
455455
return Success;
@@ -1655,7 +1655,7 @@ DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID,
16551655
if (RegNo & 0x1)
16561656
return Fail;
16571657

1658-
unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2);
1658+
MCRegister Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2);
16591659
Inst.addOperand(MCOperand::createReg(Reg));
16601660
return Success;
16611661
}

‎llvm/lib/Target/AMDGPU/R600InstrInfo.cpp

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1062,7 +1062,8 @@ void R600InstrInfo::reserveIndirectRegisters(BitVector &Reserved,
10621062

10631063
for (int Index = getIndirectIndexBegin(MF); Index <= End; ++Index) {
10641064
for (unsigned Chan = 0; Chan < StackWidth; ++Chan) {
1065-
unsigned Reg = R600::R600_TReg32RegClass.getRegister((4 * Index) + Chan);
1065+
MCRegister Reg =
1066+
R600::R600_TReg32RegClass.getRegister((4 * Index) + Chan);
10661067
TRI.reserveRegisterTuples(Reserved, Reg);
10671068
}
10681069
}
@@ -1084,7 +1085,7 @@ MachineInstrBuilder R600InstrInfo::buildIndirectWrite(MachineBasicBlock *MBB,
10841085
unsigned ValueReg, unsigned Address,
10851086
unsigned OffsetReg,
10861087
unsigned AddrChan) const {
1087-
unsigned AddrReg;
1088+
MCRegister AddrReg;
10881089
switch (AddrChan) {
10891090
default: llvm_unreachable("Invalid Channel");
10901091
case 0: AddrReg = R600::R600_AddrRegClass.getRegister(Address); break;
@@ -1116,7 +1117,7 @@ MachineInstrBuilder R600InstrInfo::buildIndirectRead(MachineBasicBlock *MBB,
11161117
unsigned ValueReg, unsigned Address,
11171118
unsigned OffsetReg,
11181119
unsigned AddrChan) const {
1119-
unsigned AddrReg;
1120+
MCRegister AddrReg;
11201121
switch (AddrChan) {
11211122
default: llvm_unreachable("Invalid Channel");
11221123
case 0: AddrReg = R600::R600_AddrRegClass.getRegister(Address); break;

‎llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6983,7 +6983,7 @@ void ARMAsmParser::fixupGNULDRDAlias(StringRef Mnemonic,
69836983
}
69846984
if (Op2.getReg() == ARM::PC)
69856985
return;
6986-
unsigned PairedReg = GPR.getRegister(RtEncoding + 1);
6986+
MCRegister PairedReg = GPR.getRegister(RtEncoding + 1);
69876987
if (!PairedReg || PairedReg == ARM::PC ||
69886988
(PairedReg == ARM::SP && !hasV8Ops()))
69896989
return;

‎llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -856,7 +856,7 @@ class MipsOperand : public MCParsedAsmOperand {
856856
public:
857857
/// Coerce the register to GPR32 and return the real register for the current
858858
/// target.
859-
unsigned getGPR32Reg() const {
859+
MCRegister getGPR32Reg() const {
860860
assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");
861861
AsmParser.warnIfRegIndexIsAT(RegIdx.Index, StartLoc);
862862
unsigned ClassID = Mips::GPR32RegClassID;
@@ -865,15 +865,15 @@ class MipsOperand : public MCParsedAsmOperand {
865865

866866
/// Coerce the register to GPR32 and return the real register for the current
867867
/// target.
868-
unsigned getGPRMM16Reg() const {
868+
MCRegister getGPRMM16Reg() const {
869869
assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");
870870
unsigned ClassID = Mips::GPR32RegClassID;
871871
return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
872872
}
873873

874874
/// Coerce the register to GPR64 and return the real register for the current
875875
/// target.
876-
unsigned getGPR64Reg() const {
876+
MCRegister getGPR64Reg() const {
877877
assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");
878878
unsigned ClassID = Mips::GPR64RegClassID;
879879
return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
@@ -882,7 +882,7 @@ class MipsOperand : public MCParsedAsmOperand {
882882
private:
883883
/// Coerce the register to AFGR64 and return the real register for the current
884884
/// target.
885-
unsigned getAFGR64Reg() const {
885+
MCRegister getAFGR64Reg() const {
886886
assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
887887
if (RegIdx.Index % 2 != 0)
888888
AsmParser.Warning(StartLoc, "Float register should be even.");
@@ -892,31 +892,31 @@ class MipsOperand : public MCParsedAsmOperand {
892892

893893
/// Coerce the register to FGR64 and return the real register for the current
894894
/// target.
895-
unsigned getFGR64Reg() const {
895+
MCRegister getFGR64Reg() const {
896896
assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
897897
return RegIdx.RegInfo->getRegClass(Mips::FGR64RegClassID)
898898
.getRegister(RegIdx.Index);
899899
}
900900

901901
/// Coerce the register to FGR32 and return the real register for the current
902902
/// target.
903-
unsigned getFGR32Reg() const {
903+
MCRegister getFGR32Reg() const {
904904
assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
905905
return RegIdx.RegInfo->getRegClass(Mips::FGR32RegClassID)
906906
.getRegister(RegIdx.Index);
907907
}
908908

909909
/// Coerce the register to FCC and return the real register for the current
910910
/// target.
911-
unsigned getFCCReg() const {
911+
MCRegister getFCCReg() const {
912912
assert(isRegIdx() && (RegIdx.Kind & RegKind_FCC) && "Invalid access!");
913913
return RegIdx.RegInfo->getRegClass(Mips::FCCRegClassID)
914914
.getRegister(RegIdx.Index);
915915
}
916916

917917
/// Coerce the register to MSA128 and return the real register for the current
918918
/// target.
919-
unsigned getMSA128Reg() const {
919+
MCRegister getMSA128Reg() const {
920920
assert(isRegIdx() && (RegIdx.Kind & RegKind_MSA128) && "Invalid access!");
921921
// It doesn't matter which of the MSA128[BHWD] classes we use. They are all
922922
// identical
@@ -926,71 +926,71 @@ class MipsOperand : public MCParsedAsmOperand {
926926

927927
/// Coerce the register to MSACtrl and return the real register for the
928928
/// current target.
929-
unsigned getMSACtrlReg() const {
929+
MCRegister getMSACtrlReg() const {
930930
assert(isRegIdx() && (RegIdx.Kind & RegKind_MSACtrl) && "Invalid access!");
931931
unsigned ClassID = Mips::MSACtrlRegClassID;
932932
return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
933933
}
934934

935935
/// Coerce the register to COP0 and return the real register for the
936936
/// current target.
937-
unsigned getCOP0Reg() const {
937+
MCRegister getCOP0Reg() const {
938938
assert(isRegIdx() && (RegIdx.Kind & RegKind_COP0) && "Invalid access!");
939939
unsigned ClassID = Mips::COP0RegClassID;
940940
return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
941941
}
942942

943943
/// Coerce the register to COP2 and return the real register for the
944944
/// current target.
945-
unsigned getCOP2Reg() const {
945+
MCRegister getCOP2Reg() const {
946946
assert(isRegIdx() && (RegIdx.Kind & RegKind_COP2) && "Invalid access!");
947947
unsigned ClassID = Mips::COP2RegClassID;
948948
return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
949949
}
950950

951951
/// Coerce the register to COP3 and return the real register for the
952952
/// current target.
953-
unsigned getCOP3Reg() const {
953+
MCRegister getCOP3Reg() const {
954954
assert(isRegIdx() && (RegIdx.Kind & RegKind_COP3) && "Invalid access!");
955955
unsigned ClassID = Mips::COP3RegClassID;
956956
return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
957957
}
958958

959959
/// Coerce the register to ACC64DSP and return the real register for the
960960
/// current target.
961-
unsigned getACC64DSPReg() const {
961+
MCRegister getACC64DSPReg() const {
962962
assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!");
963963
unsigned ClassID = Mips::ACC64DSPRegClassID;
964964
return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
965965
}
966966

967967
/// Coerce the register to HI32DSP and return the real register for the
968968
/// current target.
969-
unsigned getHI32DSPReg() const {
969+
MCRegister getHI32DSPReg() const {
970970
assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!");
971971
unsigned ClassID = Mips::HI32DSPRegClassID;
972972
return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
973973
}
974974

975975
/// Coerce the register to LO32DSP and return the real register for the
976976
/// current target.
977-
unsigned getLO32DSPReg() const {
977+
MCRegister getLO32DSPReg() const {
978978
assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!");
979979
unsigned ClassID = Mips::LO32DSPRegClassID;
980980
return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
981981
}
982982

983983
/// Coerce the register to CCR and return the real register for the
984984
/// current target.
985-
unsigned getCCRReg() const {
985+
MCRegister getCCRReg() const {
986986
assert(isRegIdx() && (RegIdx.Kind & RegKind_CCR) && "Invalid access!");
987987
unsigned ClassID = Mips::CCRRegClassID;
988988
return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
989989
}
990990

991991
/// Coerce the register to HWRegs and return the real register for the
992992
/// current target.
993-
unsigned getHWRegsReg() const {
993+
MCRegister getHWRegsReg() const {
994994
assert(isRegIdx() && (RegIdx.Kind & RegKind_HWRegs) && "Invalid access!");
995995
unsigned ClassID = Mips::HWRegsRegClassID;
996996
return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);

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