@@ -856,7 +856,7 @@ class MipsOperand : public MCParsedAsmOperand {
856856public:
857857 /// Coerce the register to GPR32 and return the real register for the current
858858 /// target.
859- unsigned getGPR32Reg() const {
859+ MCRegister getGPR32Reg() const {
860860 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");
861861 AsmParser.warnIfRegIndexIsAT(RegIdx.Index, StartLoc);
862862 unsigned ClassID = Mips::GPR32RegClassID;
@@ -865,15 +865,15 @@ class MipsOperand : public MCParsedAsmOperand {
865865
866866 /// Coerce the register to GPR32 and return the real register for the current
867867 /// target.
868- unsigned getGPRMM16Reg() const {
868+ MCRegister getGPRMM16Reg() const {
869869 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");
870870 unsigned ClassID = Mips::GPR32RegClassID;
871871 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
872872 }
873873
874874 /// Coerce the register to GPR64 and return the real register for the current
875875 /// target.
876- unsigned getGPR64Reg() const {
876+ MCRegister getGPR64Reg() const {
877877 assert(isRegIdx() && (RegIdx.Kind & RegKind_GPR) && "Invalid access!");
878878 unsigned ClassID = Mips::GPR64RegClassID;
879879 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
@@ -882,7 +882,7 @@ class MipsOperand : public MCParsedAsmOperand {
882882private:
883883 /// Coerce the register to AFGR64 and return the real register for the current
884884 /// target.
885- unsigned getAFGR64Reg() const {
885+ MCRegister getAFGR64Reg() const {
886886 assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
887887 if (RegIdx.Index % 2 != 0)
888888 AsmParser.Warning(StartLoc, "Float register should be even.");
@@ -892,31 +892,31 @@ class MipsOperand : public MCParsedAsmOperand {
892892
893893 /// Coerce the register to FGR64 and return the real register for the current
894894 /// target.
895- unsigned getFGR64Reg() const {
895+ MCRegister getFGR64Reg() const {
896896 assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
897897 return RegIdx.RegInfo->getRegClass(Mips::FGR64RegClassID)
898898 .getRegister(RegIdx.Index);
899899 }
900900
901901 /// Coerce the register to FGR32 and return the real register for the current
902902 /// target.
903- unsigned getFGR32Reg() const {
903+ MCRegister getFGR32Reg() const {
904904 assert(isRegIdx() && (RegIdx.Kind & RegKind_FGR) && "Invalid access!");
905905 return RegIdx.RegInfo->getRegClass(Mips::FGR32RegClassID)
906906 .getRegister(RegIdx.Index);
907907 }
908908
909909 /// Coerce the register to FCC and return the real register for the current
910910 /// target.
911- unsigned getFCCReg() const {
911+ MCRegister getFCCReg() const {
912912 assert(isRegIdx() && (RegIdx.Kind & RegKind_FCC) && "Invalid access!");
913913 return RegIdx.RegInfo->getRegClass(Mips::FCCRegClassID)
914914 .getRegister(RegIdx.Index);
915915 }
916916
917917 /// Coerce the register to MSA128 and return the real register for the current
918918 /// target.
919- unsigned getMSA128Reg() const {
919+ MCRegister getMSA128Reg() const {
920920 assert(isRegIdx() && (RegIdx.Kind & RegKind_MSA128) && "Invalid access!");
921921 // It doesn't matter which of the MSA128[BHWD] classes we use. They are all
922922 // identical
@@ -926,71 +926,71 @@ class MipsOperand : public MCParsedAsmOperand {
926926
927927 /// Coerce the register to MSACtrl and return the real register for the
928928 /// current target.
929- unsigned getMSACtrlReg() const {
929+ MCRegister getMSACtrlReg() const {
930930 assert(isRegIdx() && (RegIdx.Kind & RegKind_MSACtrl) && "Invalid access!");
931931 unsigned ClassID = Mips::MSACtrlRegClassID;
932932 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
933933 }
934934
935935 /// Coerce the register to COP0 and return the real register for the
936936 /// current target.
937- unsigned getCOP0Reg() const {
937+ MCRegister getCOP0Reg() const {
938938 assert(isRegIdx() && (RegIdx.Kind & RegKind_COP0) && "Invalid access!");
939939 unsigned ClassID = Mips::COP0RegClassID;
940940 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
941941 }
942942
943943 /// Coerce the register to COP2 and return the real register for the
944944 /// current target.
945- unsigned getCOP2Reg() const {
945+ MCRegister getCOP2Reg() const {
946946 assert(isRegIdx() && (RegIdx.Kind & RegKind_COP2) && "Invalid access!");
947947 unsigned ClassID = Mips::COP2RegClassID;
948948 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
949949 }
950950
951951 /// Coerce the register to COP3 and return the real register for the
952952 /// current target.
953- unsigned getCOP3Reg() const {
953+ MCRegister getCOP3Reg() const {
954954 assert(isRegIdx() && (RegIdx.Kind & RegKind_COP3) && "Invalid access!");
955955 unsigned ClassID = Mips::COP3RegClassID;
956956 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
957957 }
958958
959959 /// Coerce the register to ACC64DSP and return the real register for the
960960 /// current target.
961- unsigned getACC64DSPReg() const {
961+ MCRegister getACC64DSPReg() const {
962962 assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!");
963963 unsigned ClassID = Mips::ACC64DSPRegClassID;
964964 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
965965 }
966966
967967 /// Coerce the register to HI32DSP and return the real register for the
968968 /// current target.
969- unsigned getHI32DSPReg() const {
969+ MCRegister getHI32DSPReg() const {
970970 assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!");
971971 unsigned ClassID = Mips::HI32DSPRegClassID;
972972 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
973973 }
974974
975975 /// Coerce the register to LO32DSP and return the real register for the
976976 /// current target.
977- unsigned getLO32DSPReg() const {
977+ MCRegister getLO32DSPReg() const {
978978 assert(isRegIdx() && (RegIdx.Kind & RegKind_ACC) && "Invalid access!");
979979 unsigned ClassID = Mips::LO32DSPRegClassID;
980980 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
981981 }
982982
983983 /// Coerce the register to CCR and return the real register for the
984984 /// current target.
985- unsigned getCCRReg() const {
985+ MCRegister getCCRReg() const {
986986 assert(isRegIdx() && (RegIdx.Kind & RegKind_CCR) && "Invalid access!");
987987 unsigned ClassID = Mips::CCRRegClassID;
988988 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
989989 }
990990
991991 /// Coerce the register to HWRegs and return the real register for the
992992 /// current target.
993- unsigned getHWRegsReg() const {
993+ MCRegister getHWRegsReg() const {
994994 assert(isRegIdx() && (RegIdx.Kind & RegKind_HWRegs) && "Invalid access!");
995995 unsigned ClassID = Mips::HWRegsRegClassID;
996996 return RegIdx.RegInfo->getRegClass(ClassID).getRegister(RegIdx.Index);
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