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el-evel-ev
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update affected tests
1 parent 726a550 commit 976f717

12 files changed

+811
-932
lines changed

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 2 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -8119,13 +8119,10 @@ static SDValue foldMaskedMergeImpl(SDValue AndL0, SDValue AndR0, SDValue AndL1,
81198119
if (NotOp != AndL1)
81208120
return SDValue();
81218121

8122-
// (~(NotOp) & And0_R) | (NotOp & And1_R)
8123-
// --> ((And0_R ^ And1_R) & NotOp) ^ And1_R
81248122
EVT VT = AndL1->getValueType(0);
8125-
SDValue FreezeAndR0 = DAG.getNode(ISD::FREEZE, SDLoc(), VT, AndR0);
8126-
SDValue Xor0 = DAG.getNode(ISD::XOR, DL, VT, AndR1, FreezeAndR0);
8123+
SDValue Xor0 = DAG.getNode(ISD::XOR, DL, VT, AndR1, AndR0);
81278124
SDValue And = DAG.getNode(ISD::AND, DL, VT, Xor0, NotOp);
8128-
SDValue Xor1 = DAG.getNode(ISD::XOR, DL, VT, And, FreezeAndR0);
8125+
SDValue Xor1 = DAG.getNode(ISD::XOR, DL, VT, And, AndR0);
81298126
return Xor1;
81308127
}
81318128

‎llvm/lib/Target/SystemZ/SystemZISelLowering.cpp

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1296,6 +1296,12 @@ bool SystemZTargetLowering::allowsMisalignedMemoryAccesses(
12961296
return true;
12971297
}
12981298

1299+
bool SystemZTargetLowering::hasAndNot(SDValue Y) const {
1300+
// requires VNC instruction
1301+
return Subtarget.hasVector() &&
1302+
Y.getValueType().getScalarSizeInBits() <= 128;
1303+
}
1304+
12991305
// Information about the addressing mode for a memory access.
13001306
struct AddressingMode {
13011307
// True if a long displacement is supported.

‎llvm/lib/Target/SystemZ/SystemZISelLowering.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -671,6 +671,8 @@ class SystemZTargetLowering : public TargetLowering {
671671
}
672672

673673
unsigned getStackProbeSize(const MachineFunction &MF) const;
674+
bool hasAndNot(SDValue Y) const override;
675+
674676

675677
private:
676678
const SystemZSubtarget &Subtarget;

‎llvm/test/CodeGen/AMDGPU/bfi_int.ll

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -16,9 +16,9 @@ define amdgpu_kernel void @s_bfi_def_i32(ptr addrspace(1) %out, i32 %x, i32 %y,
1616
; GFX7-NEXT: s_mov_b32 s7, 0xf000
1717
; GFX7-NEXT: s_mov_b32 s6, -1
1818
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
19-
; GFX7-NEXT: s_andn2_b32 s2, s2, s0
19+
; GFX7-NEXT: s_xor_b32 s1, s1, s2
2020
; GFX7-NEXT: s_and_b32 s0, s1, s0
21-
; GFX7-NEXT: s_or_b32 s0, s2, s0
21+
; GFX7-NEXT: s_xor_b32 s0, s0, s2
2222
; GFX7-NEXT: v_mov_b32_e32 v0, s0
2323
; GFX7-NEXT: buffer_store_dword v0, off, s[4:7], 0
2424
; GFX7-NEXT: s_endpgm
@@ -28,9 +28,9 @@ define amdgpu_kernel void @s_bfi_def_i32(ptr addrspace(1) %out, i32 %x, i32 %y,
2828
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
2929
; GFX8-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
3030
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
31-
; GFX8-NEXT: s_andn2_b32 s2, s2, s0
31+
; GFX8-NEXT: s_xor_b32 s1, s1, s2
3232
; GFX8-NEXT: s_and_b32 s0, s1, s0
33-
; GFX8-NEXT: s_or_b32 s0, s2, s0
33+
; GFX8-NEXT: s_xor_b32 s0, s0, s2
3434
; GFX8-NEXT: v_mov_b32_e32 v0, s4
3535
; GFX8-NEXT: v_mov_b32_e32 v1, s5
3636
; GFX8-NEXT: v_mov_b32_e32 v2, s0
@@ -44,9 +44,9 @@ define amdgpu_kernel void @s_bfi_def_i32(ptr addrspace(1) %out, i32 %x, i32 %y,
4444
; GFX10-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
4545
; GFX10-NEXT: v_mov_b32_e32 v0, 0
4646
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
47-
; GFX10-NEXT: s_andn2_b32 s2, s2, s0
47+
; GFX10-NEXT: s_xor_b32 s1, s1, s2
4848
; GFX10-NEXT: s_and_b32 s0, s1, s0
49-
; GFX10-NEXT: s_or_b32 s0, s2, s0
49+
; GFX10-NEXT: s_xor_b32 s0, s0, s2
5050
; GFX10-NEXT: v_mov_b32_e32 v1, s0
5151
; GFX10-NEXT: global_store_dword v0, v1, s[4:5]
5252
; GFX10-NEXT: s_endpgm
@@ -1407,9 +1407,9 @@ define amdgpu_kernel void @s_bitselect_i64_pat_0(i64 %a, i64 %b, i64 %mask) {
14071407
; GFX7-NEXT: s_mov_b32 s7, 0xf000
14081408
; GFX7-NEXT: s_mov_b32 s6, -1
14091409
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
1410-
; GFX7-NEXT: s_and_b64 s[2:3], s[0:1], s[2:3]
1411-
; GFX7-NEXT: s_andn2_b64 s[0:1], s[4:5], s[0:1]
1412-
; GFX7-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]
1410+
; GFX7-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5]
1411+
; GFX7-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1]
1412+
; GFX7-NEXT: s_xor_b64 s[0:1], s[0:1], s[4:5]
14131413
; GFX7-NEXT: s_add_u32 s0, s0, 10
14141414
; GFX7-NEXT: s_addc_u32 s1, s1, 0
14151415
; GFX7-NEXT: v_mov_b32_e32 v0, s0
@@ -1422,9 +1422,9 @@ define amdgpu_kernel void @s_bitselect_i64_pat_0(i64 %a, i64 %b, i64 %mask) {
14221422
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
14231423
; GFX8-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
14241424
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
1425-
; GFX8-NEXT: s_and_b64 s[2:3], s[0:1], s[2:3]
1426-
; GFX8-NEXT: s_andn2_b64 s[0:1], s[4:5], s[0:1]
1427-
; GFX8-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]
1425+
; GFX8-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5]
1426+
; GFX8-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1]
1427+
; GFX8-NEXT: s_xor_b64 s[0:1], s[0:1], s[4:5]
14281428
; GFX8-NEXT: s_add_u32 s0, s0, 10
14291429
; GFX8-NEXT: s_addc_u32 s1, s1, 0
14301430
; GFX8-NEXT: v_mov_b32_e32 v0, s0
@@ -1438,9 +1438,9 @@ define amdgpu_kernel void @s_bitselect_i64_pat_0(i64 %a, i64 %b, i64 %mask) {
14381438
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
14391439
; GFX10-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
14401440
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
1441-
; GFX10-NEXT: s_and_b64 s[2:3], s[0:1], s[2:3]
1442-
; GFX10-NEXT: s_andn2_b64 s[0:1], s[4:5], s[0:1]
1443-
; GFX10-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]
1441+
; GFX10-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5]
1442+
; GFX10-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1]
1443+
; GFX10-NEXT: s_xor_b64 s[0:1], s[0:1], s[4:5]
14441444
; GFX10-NEXT: s_add_u32 s0, s0, 10
14451445
; GFX10-NEXT: s_addc_u32 s1, s1, 0
14461446
; GFX10-NEXT: v_mov_b32_e32 v0, s0

‎llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll

Lines changed: 21 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -289,16 +289,16 @@ entry:
289289
define amdgpu_kernel void @half4_inselt(ptr addrspace(1) %out, <4 x half> %vec, i32 %sel) {
290290
; GCN-LABEL: half4_inselt:
291291
; GCN: ; %bb.0: ; %entry
292-
; GCN-NEXT: s_load_dword s6, s[4:5], 0x34
293292
; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
293+
; GCN-NEXT: s_load_dword s6, s[4:5], 0x34
294294
; GCN-NEXT: s_mov_b32 s4, 0x3c003c00
295295
; GCN-NEXT: s_mov_b32 s5, s4
296296
; GCN-NEXT: s_waitcnt lgkmcnt(0)
297+
; GCN-NEXT: s_xor_b64 s[4:5], s[2:3], s[4:5]
297298
; GCN-NEXT: s_lshl_b32 s6, s6, 4
298299
; GCN-NEXT: s_lshl_b64 s[6:7], 0xffff, s6
299-
; GCN-NEXT: s_andn2_b64 s[2:3], s[2:3], s[6:7]
300-
; GCN-NEXT: s_and_b64 s[4:5], s[6:7], s[4:5]
301-
; GCN-NEXT: s_or_b64 s[2:3], s[4:5], s[2:3]
300+
; GCN-NEXT: s_and_b64 s[4:5], s[4:5], s[6:7]
301+
; GCN-NEXT: s_xor_b64 s[2:3], s[4:5], s[2:3]
302302
; GCN-NEXT: v_mov_b32_e32 v0, s0
303303
; GCN-NEXT: v_mov_b32_e32 v2, s2
304304
; GCN-NEXT: v_mov_b32_e32 v1, s1
@@ -317,10 +317,10 @@ define amdgpu_kernel void @half2_inselt(ptr addrspace(1) %out, <2 x half> %vec,
317317
; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
318318
; GCN-NEXT: s_waitcnt lgkmcnt(0)
319319
; GCN-NEXT: s_lshl_b32 s3, s3, 4
320+
; GCN-NEXT: s_xor_b32 s4, s2, 0x3c003c00
320321
; GCN-NEXT: s_lshl_b32 s3, 0xffff, s3
321-
; GCN-NEXT: s_andn2_b32 s2, s2, s3
322-
; GCN-NEXT: s_and_b32 s3, s3, 0x3c003c00
323-
; GCN-NEXT: s_or_b32 s2, s3, s2
322+
; GCN-NEXT: s_and_b32 s3, s4, s3
323+
; GCN-NEXT: s_xor_b32 s2, s3, s2
324324
; GCN-NEXT: v_mov_b32_e32 v0, s0
325325
; GCN-NEXT: v_mov_b32_e32 v1, s1
326326
; GCN-NEXT: v_mov_b32_e32 v2, s2
@@ -400,10 +400,10 @@ define amdgpu_kernel void @short2_inselt(ptr addrspace(1) %out, <2 x i16> %vec,
400400
; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
401401
; GCN-NEXT: s_waitcnt lgkmcnt(0)
402402
; GCN-NEXT: s_lshl_b32 s3, s3, 4
403+
; GCN-NEXT: s_xor_b32 s4, s2, 0x10001
403404
; GCN-NEXT: s_lshl_b32 s3, 0xffff, s3
404-
; GCN-NEXT: s_andn2_b32 s2, s2, s3
405-
; GCN-NEXT: s_and_b32 s3, s3, 0x10001
406-
; GCN-NEXT: s_or_b32 s2, s3, s2
405+
; GCN-NEXT: s_and_b32 s3, s4, s3
406+
; GCN-NEXT: s_xor_b32 s2, s3, s2
407407
; GCN-NEXT: v_mov_b32_e32 v0, s0
408408
; GCN-NEXT: v_mov_b32_e32 v1, s1
409409
; GCN-NEXT: v_mov_b32_e32 v2, s2
@@ -418,16 +418,16 @@ entry:
418418
define amdgpu_kernel void @short4_inselt(ptr addrspace(1) %out, <4 x i16> %vec, i32 %sel) {
419419
; GCN-LABEL: short4_inselt:
420420
; GCN: ; %bb.0: ; %entry
421-
; GCN-NEXT: s_load_dword s6, s[4:5], 0x34
422421
; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
422+
; GCN-NEXT: s_load_dword s6, s[4:5], 0x34
423423
; GCN-NEXT: s_mov_b32 s4, 0x10001
424424
; GCN-NEXT: s_mov_b32 s5, s4
425425
; GCN-NEXT: s_waitcnt lgkmcnt(0)
426+
; GCN-NEXT: s_xor_b64 s[4:5], s[2:3], s[4:5]
426427
; GCN-NEXT: s_lshl_b32 s6, s6, 4
427428
; GCN-NEXT: s_lshl_b64 s[6:7], 0xffff, s6
428-
; GCN-NEXT: s_andn2_b64 s[2:3], s[2:3], s[6:7]
429-
; GCN-NEXT: s_and_b64 s[4:5], s[6:7], s[4:5]
430-
; GCN-NEXT: s_or_b64 s[2:3], s[4:5], s[2:3]
429+
; GCN-NEXT: s_and_b64 s[4:5], s[4:5], s[6:7]
430+
; GCN-NEXT: s_xor_b64 s[2:3], s[4:5], s[2:3]
431431
; GCN-NEXT: v_mov_b32_e32 v0, s0
432432
; GCN-NEXT: v_mov_b32_e32 v2, s2
433433
; GCN-NEXT: v_mov_b32_e32 v1, s1
@@ -443,15 +443,15 @@ entry:
443443
define amdgpu_kernel void @byte8_inselt(ptr addrspace(1) %out, <8 x i8> %vec, i32 %sel) {
444444
; GCN-LABEL: byte8_inselt:
445445
; GCN: ; %bb.0: ; %entry
446-
; GCN-NEXT: s_load_dword s6, s[4:5], 0x34
447446
; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
447+
; GCN-NEXT: s_load_dword s6, s[4:5], 0x34
448448
; GCN-NEXT: s_waitcnt lgkmcnt(0)
449-
; GCN-NEXT: s_lshl_b32 s4, s6, 3
450-
; GCN-NEXT: s_lshl_b64 s[4:5], 0xff, s4
451-
; GCN-NEXT: s_and_b32 s7, s5, 0x1010101
452-
; GCN-NEXT: s_and_b32 s6, s4, 0x1010101
453-
; GCN-NEXT: s_andn2_b64 s[2:3], s[2:3], s[4:5]
454-
; GCN-NEXT: s_or_b64 s[2:3], s[6:7], s[2:3]
449+
; GCN-NEXT: s_xor_b32 s5, s3, 0x1010101
450+
; GCN-NEXT: s_lshl_b32 s6, s6, 3
451+
; GCN-NEXT: s_xor_b32 s4, s2, 0x1010101
452+
; GCN-NEXT: s_lshl_b64 s[6:7], 0xff, s6
453+
; GCN-NEXT: s_and_b64 s[4:5], s[4:5], s[6:7]
454+
; GCN-NEXT: s_xor_b64 s[2:3], s[4:5], s[2:3]
455455
; GCN-NEXT: v_mov_b32_e32 v0, s0
456456
; GCN-NEXT: v_mov_b32_e32 v2, s2
457457
; GCN-NEXT: v_mov_b32_e32 v1, s1

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