Skip to content

Commit 9833332

Browse files
RKSimonRKSimon
committed
[X86] bypass-slow-division-64.ll - extend cpu test coverage
Ensure we test with/without the idivq-to-divl attribute, and test the x86-64-v* cpu levels and some common Intel/AMD cpus
1 parent 72eaa0e commit 9833332

File tree

1 file changed

+102
-56
lines changed

1 file changed

+102
-56
lines changed

‎llvm/test/CodeGen/X86/bypass-slow-division-64.ll

Lines changed: 102 additions & 56 deletions
Original file line numberDiff line numberDiff line change
@@ -1,75 +1,121 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; Check that 64-bit division is bypassed correctly.
3-
; RUN: llc < %s -mattr=+idivq-to-divl -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
3+
; RUN: llc < %s -mtriple=x86_64-- -mattr=-idivq-to-divl | FileCheck %s --check-prefixes=CHECK,FAST-DIVQ
4+
; RUN: llc < %s -mtriple=x86_64-- -mattr=+idivq-to-divl | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ
5+
; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ
6+
; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v2 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ
7+
; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ
8+
; RUN: llc < %s -mtriple=x86_64-- -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ
9+
; Intel
10+
; RUN: llc < %s -mtriple=x86_64-- -mcpu=nehalem | FileCheck %s --check-prefixes=CHECK,FAST-DIVQ
11+
; RUN: llc < %s -mtriple=x86_64-- -mcpu=sandybridge | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ
12+
; RUN: llc < %s -mtriple=x86_64-- -mcpu=haswell | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ
13+
; RUN: llc < %s -mtriple=x86_64-- -mcpu=skylake | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ
14+
; RUN: llc < %s -mtriple=x86_64-- -mcpu=alderlake | FileCheck %s --check-prefixes=CHECK,SLOW-DIVQ
15+
; AMD
16+
; RUN: llc < %s -mtriple=x86_64-- -mcpu=barcelona | FileCheck %s --check-prefixes=CHECK,FAST-DIVQ
17+
; RUN: llc < %s -mtriple=x86_64-- -mcpu=btver1 | FileCheck %s --check-prefixes=CHECK,FAST-DIVQ
18+
; RUN: llc < %s -mtriple=x86_64-- -mcpu=btver2 | FileCheck %s --check-prefixes=CHECK,FAST-DIVQ
19+
; RUN: llc < %s -mtriple=x86_64-- -mcpu=bdver1 | FileCheck %s --check-prefixes=CHECK,FAST-DIVQ
20+
; RUN: llc < %s -mtriple=x86_64-- -mcpu=bdver2 | FileCheck %s --check-prefixes=CHECK,FAST-DIVQ
21+
; RUN: llc < %s -mtriple=x86_64-- -mcpu=bdver3 | FileCheck %s --check-prefixes=CHECK,FAST-DIVQ
22+
; RUN: llc < %s -mtriple=x86_64-- -mcpu=bdver4 | FileCheck %s --check-prefixes=CHECK,FAST-DIVQ
23+
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver1 | FileCheck %s --check-prefixes=CHECK,FAST-DIVQ
24+
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver2 | FileCheck %s --check-prefixes=CHECK,FAST-DIVQ
25+
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver3 | FileCheck %s --check-prefixes=CHECK,FAST-DIVQ
26+
; RUN: llc < %s -mtriple=x86_64-- -mcpu=znver4 | FileCheck %s --check-prefixes=CHECK,FAST-DIVQ
427

528
; Additional tests for 64-bit divide bypass
629

730
define i64 @Test_get_quotient(i64 %a, i64 %b) nounwind {
8-
; CHECK-LABEL: Test_get_quotient:
9-
; CHECK: # %bb.0:
10-
; CHECK-NEXT: movq %rdi, %rax
11-
; CHECK-NEXT: movq %rdi, %rcx
12-
; CHECK-NEXT: orq %rsi, %rcx
13-
; CHECK-NEXT: shrq $32, %rcx
14-
; CHECK-NEXT: je .LBB0_1
15-
; CHECK-NEXT: # %bb.2:
16-
; CHECK-NEXT: cqto
17-
; CHECK-NEXT: idivq %rsi
18-
; CHECK-NEXT: retq
19-
; CHECK-NEXT: .LBB0_1:
20-
; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
21-
; CHECK-NEXT: xorl %edx, %edx
22-
; CHECK-NEXT: divl %esi
23-
; CHECK-NEXT: # kill: def $eax killed $eax def $rax
24-
; CHECK-NEXT: retq
31+
; FAST-DIVQ-LABEL: Test_get_quotient:
32+
; FAST-DIVQ: # %bb.0:
33+
; FAST-DIVQ-NEXT: movq %rdi, %rax
34+
; FAST-DIVQ-NEXT: cqto
35+
; FAST-DIVQ-NEXT: idivq %rsi
36+
; FAST-DIVQ-NEXT: retq
37+
;
38+
; SLOW-DIVQ-LABEL: Test_get_quotient:
39+
; SLOW-DIVQ: # %bb.0:
40+
; SLOW-DIVQ-NEXT: movq %rdi, %rax
41+
; SLOW-DIVQ-NEXT: movq %rdi, %rcx
42+
; SLOW-DIVQ-NEXT: orq %rsi, %rcx
43+
; SLOW-DIVQ-NEXT: shrq $32, %rcx
44+
; SLOW-DIVQ-NEXT: je .LBB0_1
45+
; SLOW-DIVQ-NEXT: # %bb.2:
46+
; SLOW-DIVQ-NEXT: cqto
47+
; SLOW-DIVQ-NEXT: idivq %rsi
48+
; SLOW-DIVQ-NEXT: retq
49+
; SLOW-DIVQ-NEXT: .LBB0_1:
50+
; SLOW-DIVQ-NEXT: # kill: def $eax killed $eax killed $rax
51+
; SLOW-DIVQ-NEXT: xorl %edx, %edx
52+
; SLOW-DIVQ-NEXT: divl %esi
53+
; SLOW-DIVQ-NEXT: # kill: def $eax killed $eax def $rax
54+
; SLOW-DIVQ-NEXT: retq
2555
%result = sdiv i64 %a, %b
2656
ret i64 %result
2757
}
2858

2959
define i64 @Test_get_remainder(i64 %a, i64 %b) nounwind {
30-
; CHECK-LABEL: Test_get_remainder:
31-
; CHECK: # %bb.0:
32-
; CHECK-NEXT: movq %rdi, %rax
33-
; CHECK-NEXT: movq %rdi, %rcx
34-
; CHECK-NEXT: orq %rsi, %rcx
35-
; CHECK-NEXT: shrq $32, %rcx
36-
; CHECK-NEXT: je .LBB1_1
37-
; CHECK-NEXT: # %bb.2:
38-
; CHECK-NEXT: cqto
39-
; CHECK-NEXT: idivq %rsi
40-
; CHECK-NEXT: movq %rdx, %rax
41-
; CHECK-NEXT: retq
42-
; CHECK-NEXT: .LBB1_1:
43-
; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
44-
; CHECK-NEXT: xorl %edx, %edx
45-
; CHECK-NEXT: divl %esi
46-
; CHECK-NEXT: movl %edx, %eax
47-
; CHECK-NEXT: retq
60+
; FAST-DIVQ-LABEL: Test_get_remainder:
61+
; FAST-DIVQ: # %bb.0:
62+
; FAST-DIVQ-NEXT: movq %rdi, %rax
63+
; FAST-DIVQ-NEXT: cqto
64+
; FAST-DIVQ-NEXT: idivq %rsi
65+
; FAST-DIVQ-NEXT: movq %rdx, %rax
66+
; FAST-DIVQ-NEXT: retq
67+
;
68+
; SLOW-DIVQ-LABEL: Test_get_remainder:
69+
; SLOW-DIVQ: # %bb.0:
70+
; SLOW-DIVQ-NEXT: movq %rdi, %rax
71+
; SLOW-DIVQ-NEXT: movq %rdi, %rcx
72+
; SLOW-DIVQ-NEXT: orq %rsi, %rcx
73+
; SLOW-DIVQ-NEXT: shrq $32, %rcx
74+
; SLOW-DIVQ-NEXT: je .LBB1_1
75+
; SLOW-DIVQ-NEXT: # %bb.2:
76+
; SLOW-DIVQ-NEXT: cqto
77+
; SLOW-DIVQ-NEXT: idivq %rsi
78+
; SLOW-DIVQ-NEXT: movq %rdx, %rax
79+
; SLOW-DIVQ-NEXT: retq
80+
; SLOW-DIVQ-NEXT: .LBB1_1:
81+
; SLOW-DIVQ-NEXT: # kill: def $eax killed $eax killed $rax
82+
; SLOW-DIVQ-NEXT: xorl %edx, %edx
83+
; SLOW-DIVQ-NEXT: divl %esi
84+
; SLOW-DIVQ-NEXT: movl %edx, %eax
85+
; SLOW-DIVQ-NEXT: retq
4886
%result = srem i64 %a, %b
4987
ret i64 %result
5088
}
5189

5290
define i64 @Test_get_quotient_and_remainder(i64 %a, i64 %b) nounwind {
53-
; CHECK-LABEL: Test_get_quotient_and_remainder:
54-
; CHECK: # %bb.0:
55-
; CHECK-NEXT: movq %rdi, %rax
56-
; CHECK-NEXT: movq %rdi, %rcx
57-
; CHECK-NEXT: orq %rsi, %rcx
58-
; CHECK-NEXT: shrq $32, %rcx
59-
; CHECK-NEXT: je .LBB2_1
60-
; CHECK-NEXT: # %bb.2:
61-
; CHECK-NEXT: cqto
62-
; CHECK-NEXT: idivq %rsi
63-
; CHECK-NEXT: addq %rdx, %rax
64-
; CHECK-NEXT: retq
65-
; CHECK-NEXT: .LBB2_1:
66-
; CHECK-NEXT: # kill: def $eax killed $eax killed $rax
67-
; CHECK-NEXT: xorl %edx, %edx
68-
; CHECK-NEXT: divl %esi
69-
; CHECK-NEXT: # kill: def $edx killed $edx def $rdx
70-
; CHECK-NEXT: # kill: def $eax killed $eax def $rax
71-
; CHECK-NEXT: addq %rdx, %rax
72-
; CHECK-NEXT: retq
91+
; FAST-DIVQ-LABEL: Test_get_quotient_and_remainder:
92+
; FAST-DIVQ: # %bb.0:
93+
; FAST-DIVQ-NEXT: movq %rdi, %rax
94+
; FAST-DIVQ-NEXT: cqto
95+
; FAST-DIVQ-NEXT: idivq %rsi
96+
; FAST-DIVQ-NEXT: addq %rdx, %rax
97+
; FAST-DIVQ-NEXT: retq
98+
;
99+
; SLOW-DIVQ-LABEL: Test_get_quotient_and_remainder:
100+
; SLOW-DIVQ: # %bb.0:
101+
; SLOW-DIVQ-NEXT: movq %rdi, %rax
102+
; SLOW-DIVQ-NEXT: movq %rdi, %rcx
103+
; SLOW-DIVQ-NEXT: orq %rsi, %rcx
104+
; SLOW-DIVQ-NEXT: shrq $32, %rcx
105+
; SLOW-DIVQ-NEXT: je .LBB2_1
106+
; SLOW-DIVQ-NEXT: # %bb.2:
107+
; SLOW-DIVQ-NEXT: cqto
108+
; SLOW-DIVQ-NEXT: idivq %rsi
109+
; SLOW-DIVQ-NEXT: addq %rdx, %rax
110+
; SLOW-DIVQ-NEXT: retq
111+
; SLOW-DIVQ-NEXT: .LBB2_1:
112+
; SLOW-DIVQ-NEXT: # kill: def $eax killed $eax killed $rax
113+
; SLOW-DIVQ-NEXT: xorl %edx, %edx
114+
; SLOW-DIVQ-NEXT: divl %esi
115+
; SLOW-DIVQ-NEXT: # kill: def $edx killed $edx def $rdx
116+
; SLOW-DIVQ-NEXT: # kill: def $eax killed $eax def $rax
117+
; SLOW-DIVQ-NEXT: addq %rdx, %rax
118+
; SLOW-DIVQ-NEXT: retq
73119
%resultdiv = sdiv i64 %a, %b
74120
%resultrem = srem i64 %a, %b
75121
%result = add i64 %resultdiv, %resultrem

0 commit comments

Comments
 (0)