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DavidSpickettDavidSpickett
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Revert "[AArch64][GlobalISel] Make G_DUP immediate 32-bits or larger (#96780)"
This reverts commit 5a5cd3f. Due to test suite failures on AArch64: https://lab.llvm.org/buildbot/#/builders/125/builds/541
1 parent 7293720 commit 9856af6

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6 files changed

+123
-102
lines changed

6 files changed

+123
-102
lines changed

‎llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5551,8 +5551,7 @@ AArch64InstructionSelector::emitConstantVector(Register Dst, Constant *CV,
55515551
}
55525552

55535553
if (CV->getSplatValue()) {
5554-
APInt DefBits = APInt::getSplat(
5555-
DstSize, CV->getUniqueInteger().trunc(DstTy.getScalarSizeInBits()));
5554+
APInt DefBits = APInt::getSplat(DstSize, CV->getUniqueInteger());
55565555
auto TryMOVIWithBits = [&](APInt DefBits) -> MachineInstr * {
55575556
MachineInstr *NewOp;
55585557
bool Inv = false;

‎llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp

Lines changed: 2 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -42,7 +42,6 @@
4242
#include "AArch64GenRegisterBankInfo.def"
4343

4444
using namespace llvm;
45-
static const unsigned CustomMappingID = 1;
4645

4746
AArch64RegisterBankInfo::AArch64RegisterBankInfo(
4847
const TargetRegisterInfo &TRI) {
@@ -425,27 +424,6 @@ void AArch64RegisterBankInfo::applyMappingImpl(
425424
MI.getOperand(2).setReg(Ext.getReg(0));
426425
return applyDefaultMapping(OpdMapper);
427426
}
428-
case AArch64::G_DUP: {
429-
// Extend smaller gpr to 32-bits
430-
assert(MRI.getType(MI.getOperand(1).getReg()).getSizeInBits() < 32 &&
431-
"Expected sources smaller than 32-bits");
432-
Builder.setInsertPt(*MI.getParent(), MI.getIterator());
433-
434-
Register ConstReg;
435-
auto ConstMI = MRI.getVRegDef(MI.getOperand(1).getReg());
436-
if (ConstMI->getOpcode() == TargetOpcode::G_CONSTANT) {
437-
auto CstVal = ConstMI->getOperand(1).getCImm()->getValue();
438-
ConstReg =
439-
Builder.buildConstant(LLT::scalar(32), CstVal.sext(32)).getReg(0);
440-
ConstMI->eraseFromParent();
441-
} else {
442-
ConstReg = Builder.buildAnyExt(LLT::scalar(32), MI.getOperand(1).getReg())
443-
.getReg(0);
444-
}
445-
MRI.setRegBank(ConstReg, getRegBank(AArch64::GPRRegBankID));
446-
MI.getOperand(1).setReg(ConstReg);
447-
return applyDefaultMapping(OpdMapper);
448-
}
449427
default:
450428
llvm_unreachable("Don't know how to handle that operation");
451429
}
@@ -814,13 +792,8 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
814792
(getRegBank(ScalarReg, MRI, TRI) == &AArch64::FPRRegBank ||
815793
onlyDefinesFP(*ScalarDef, MRI, TRI)))
816794
OpRegBankIdx = {PMI_FirstFPR, PMI_FirstFPR};
817-
else {
818-
if (ScalarTy.getSizeInBits() < 32 &&
819-
getRegBank(ScalarReg, MRI, TRI) == &AArch64::GPRRegBank)
820-
// Calls applyMappingImpl()
821-
MappingID = CustomMappingID;
795+
else
822796
OpRegBankIdx = {PMI_FirstFPR, PMI_FirstGPR};
823-
}
824797
break;
825798
}
826799
case TargetOpcode::G_TRUNC: {
@@ -1042,8 +1015,7 @@ AArch64RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
10421015
// type to i32 in applyMappingImpl.
10431016
LLT Ty = MRI.getType(MI.getOperand(2).getReg());
10441017
if (Ty.getSizeInBits() == 8 || Ty.getSizeInBits() == 16)
1045-
// Calls applyMappingImpl()
1046-
MappingID = CustomMappingID;
1018+
MappingID = 1;
10471019
OpRegBankIdx[2] = PMI_FirstGPR;
10481020
}
10491021

‎llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -18,8 +18,8 @@ define <8 x i16> @combine_vec_udiv_uniform(<8 x i16> %x) {
1818
;
1919
; GISEL-LABEL: combine_vec_udiv_uniform:
2020
; GISEL: // %bb.0:
21-
; GISEL-NEXT: mov w8, #25645 // =0x642d
22-
; GISEL-NEXT: dup v1.8h, w8
21+
; GISEL-NEXT: adrp x8, .LCPI0_0
22+
; GISEL-NEXT: ldr q1, [x8, :lo12:.LCPI0_0]
2323
; GISEL-NEXT: umull2 v2.4s, v0.8h, v1.8h
2424
; GISEL-NEXT: umull v1.4s, v0.4h, v1.4h
2525
; GISEL-NEXT: uzp2 v1.8h, v1.8h, v2.8h

‎llvm/test/CodeGen/AArch64/GlobalISel/regbank-dup.mir

Lines changed: 33 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -16,11 +16,10 @@ body: |
1616
1717
; CHECK-LABEL: name: v4s32_gpr
1818
; CHECK: liveins: $w0
19-
; CHECK-NEXT: {{ $}}
20-
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
21-
; CHECK-NEXT: [[DUP:%[0-9]+]]:fpr(<4 x s32>) = G_DUP [[COPY]](s32)
22-
; CHECK-NEXT: $q0 = COPY [[DUP]](<4 x s32>)
23-
; CHECK-NEXT: RET_ReallyLR implicit $q0
19+
; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
20+
; CHECK: [[DUP:%[0-9]+]]:fpr(<4 x s32>) = G_DUP [[COPY]](s32)
21+
; CHECK: $q0 = COPY [[DUP]](<4 x s32>)
22+
; CHECK: RET_ReallyLR implicit $q0
2423
%0:_(s32) = COPY $w0
2524
%4:_(<4 x s32>) = G_DUP %0(s32)
2625
$q0 = COPY %4(<4 x s32>)
@@ -38,11 +37,10 @@ body: |
3837
3938
; CHECK-LABEL: name: v4s64_gpr
4039
; CHECK: liveins: $x0
41-
; CHECK-NEXT: {{ $}}
42-
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s64) = COPY $x0
43-
; CHECK-NEXT: [[DUP:%[0-9]+]]:fpr(<2 x s64>) = G_DUP [[COPY]](s64)
44-
; CHECK-NEXT: $q0 = COPY [[DUP]](<2 x s64>)
45-
; CHECK-NEXT: RET_ReallyLR implicit $q0
40+
; CHECK: [[COPY:%[0-9]+]]:gpr(s64) = COPY $x0
41+
; CHECK: [[DUP:%[0-9]+]]:fpr(<2 x s64>) = G_DUP [[COPY]](s64)
42+
; CHECK: $q0 = COPY [[DUP]](<2 x s64>)
43+
; CHECK: RET_ReallyLR implicit $q0
4644
%0:_(s64) = COPY $x0
4745
%4:_(<2 x s64>) = G_DUP %0(s64)
4846
$q0 = COPY %4(<2 x s64>)
@@ -60,11 +58,10 @@ body: |
6058
6159
; CHECK-LABEL: name: v2s32_gpr
6260
; CHECK: liveins: $w0
63-
; CHECK-NEXT: {{ $}}
64-
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
65-
; CHECK-NEXT: [[DUP:%[0-9]+]]:fpr(<2 x s32>) = G_DUP [[COPY]](s32)
66-
; CHECK-NEXT: $d0 = COPY [[DUP]](<2 x s32>)
67-
; CHECK-NEXT: RET_ReallyLR implicit $d0
61+
; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
62+
; CHECK: [[DUP:%[0-9]+]]:fpr(<2 x s32>) = G_DUP [[COPY]](s32)
63+
; CHECK: $d0 = COPY [[DUP]](<2 x s32>)
64+
; CHECK: RET_ReallyLR implicit $d0
6865
%0:_(s32) = COPY $w0
6966
%4:_(<2 x s32>) = G_DUP %0(s32)
7067
$d0 = COPY %4(<2 x s32>)
@@ -82,11 +79,10 @@ body: |
8279
8380
; CHECK-LABEL: name: v4s32_fpr
8481
; CHECK: liveins: $s0
85-
; CHECK-NEXT: {{ $}}
86-
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0
87-
; CHECK-NEXT: [[DUP:%[0-9]+]]:fpr(<4 x s32>) = G_DUP [[COPY]](s32)
88-
; CHECK-NEXT: $q0 = COPY [[DUP]](<4 x s32>)
89-
; CHECK-NEXT: RET_ReallyLR implicit $q0
82+
; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0
83+
; CHECK: [[DUP:%[0-9]+]]:fpr(<4 x s32>) = G_DUP [[COPY]](s32)
84+
; CHECK: $q0 = COPY [[DUP]](<4 x s32>)
85+
; CHECK: RET_ReallyLR implicit $q0
9086
%0:_(s32) = COPY $s0
9187
%4:_(<4 x s32>) = G_DUP %0(s32)
9288
$q0 = COPY %4(<4 x s32>)
@@ -104,11 +100,10 @@ body: |
104100
105101
; CHECK-LABEL: name: v2s64_fpr
106102
; CHECK: liveins: $d0
107-
; CHECK-NEXT: {{ $}}
108-
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s64) = COPY $d0
109-
; CHECK-NEXT: [[DUP:%[0-9]+]]:fpr(<2 x s64>) = G_DUP [[COPY]](s64)
110-
; CHECK-NEXT: $q0 = COPY [[DUP]](<2 x s64>)
111-
; CHECK-NEXT: RET_ReallyLR implicit $q0
103+
; CHECK: [[COPY:%[0-9]+]]:fpr(s64) = COPY $d0
104+
; CHECK: [[DUP:%[0-9]+]]:fpr(<2 x s64>) = G_DUP [[COPY]](s64)
105+
; CHECK: $q0 = COPY [[DUP]](<2 x s64>)
106+
; CHECK: RET_ReallyLR implicit $q0
112107
%0:_(s64) = COPY $d0
113108
%4:_(<2 x s64>) = G_DUP %0(s64)
114109
$q0 = COPY %4(<2 x s64>)
@@ -126,11 +121,10 @@ body: |
126121
127122
; CHECK-LABEL: name: v2s32_fpr
128123
; CHECK: liveins: $s0
129-
; CHECK-NEXT: {{ $}}
130-
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0
131-
; CHECK-NEXT: [[DUP:%[0-9]+]]:fpr(<2 x s32>) = G_DUP [[COPY]](s32)
132-
; CHECK-NEXT: $d0 = COPY [[DUP]](<2 x s32>)
133-
; CHECK-NEXT: RET_ReallyLR implicit $d0
124+
; CHECK: [[COPY:%[0-9]+]]:fpr(s32) = COPY $s0
125+
; CHECK: [[DUP:%[0-9]+]]:fpr(<2 x s32>) = G_DUP [[COPY]](s32)
126+
; CHECK: $d0 = COPY [[DUP]](<2 x s32>)
127+
; CHECK: RET_ReallyLR implicit $d0
134128
%0:_(s32) = COPY $s0
135129
%4:_(<2 x s32>) = G_DUP %0(s32)
136130
$d0 = COPY %4(<2 x s32>)
@@ -148,11 +142,10 @@ body: |
148142
149143
; CHECK-LABEL: name: v2s64_fpr_copy
150144
; CHECK: liveins: $d0
151-
; CHECK-NEXT: {{ $}}
152-
; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr(s64) = COPY $d0
153-
; CHECK-NEXT: [[DUP:%[0-9]+]]:fpr(<2 x s64>) = G_DUP [[COPY]](s64)
154-
; CHECK-NEXT: $q0 = COPY [[DUP]](<2 x s64>)
155-
; CHECK-NEXT: RET_ReallyLR implicit $q0
145+
; CHECK: [[COPY:%[0-9]+]]:fpr(s64) = COPY $d0
146+
; CHECK: [[DUP:%[0-9]+]]:fpr(<2 x s64>) = G_DUP [[COPY]](s64)
147+
; CHECK: $q0 = COPY [[DUP]](<2 x s64>)
148+
; CHECK: RET_ReallyLR implicit $q0
156149
%0:_(s64) = COPY $d0
157150
%6:_(<2 x s64>) = G_DUP %0(s64)
158151
$q0 = COPY %6(<2 x s64>)
@@ -170,13 +163,11 @@ body: |
170163
171164
; CHECK-LABEL: name: v416s8_gpr
172165
; CHECK: liveins: $w0
173-
; CHECK-NEXT: {{ $}}
174-
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
175-
; CHECK-NEXT: %trunc:gpr(s8) = G_TRUNC [[COPY]](s32)
176-
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:gpr(s32) = G_ANYEXT %trunc(s8)
177-
; CHECK-NEXT: [[DUP:%[0-9]+]]:fpr(<16 x s8>) = G_DUP [[ANYEXT]](s32)
178-
; CHECK-NEXT: $q0 = COPY [[DUP]](<16 x s8>)
179-
; CHECK-NEXT: RET_ReallyLR implicit $q0
166+
; CHECK: [[COPY:%[0-9]+]]:gpr(s32) = COPY $w0
167+
; CHECK: %trunc:gpr(s8) = G_TRUNC [[COPY]](s32)
168+
; CHECK: [[DUP:%[0-9]+]]:fpr(<16 x s8>) = G_DUP %trunc(s8)
169+
; CHECK: $q0 = COPY [[DUP]](<16 x s8>)
170+
; CHECK: RET_ReallyLR implicit $q0
180171
%0:_(s32) = COPY $w0
181172
%trunc:_(s8) = G_TRUNC %0(s32)
182173
%1:_(<16 x s8>) = G_DUP %trunc(s8)

‎llvm/test/CodeGen/AArch64/aarch64-smull.ll

Lines changed: 25 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -994,9 +994,9 @@ define <8 x i16> @smull_noextvec_v8i8_v8i16(<8 x i8> %arg) nounwind {
994994
;
995995
; CHECK-GI-LABEL: smull_noextvec_v8i8_v8i16:
996996
; CHECK-GI: // %bb.0:
997-
; CHECK-GI-NEXT: mov w8, #-999 // =0xfffffc19
997+
; CHECK-GI-NEXT: adrp x8, .LCPI34_0
998998
; CHECK-GI-NEXT: sshll v0.8h, v0.8b, #0
999-
; CHECK-GI-NEXT: dup v1.8h, w8
999+
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI34_0]
10001000
; CHECK-GI-NEXT: mul v0.8h, v0.8h, v1.8h
10011001
; CHECK-GI-NEXT: ret
10021002
%tmp3 = sext <8 x i8> %arg to <8 x i16>
@@ -1088,13 +1088,29 @@ define <8 x i16> @umull_extvec_v8i8_v8i16(<8 x i8> %arg) nounwind {
10881088

10891089
define <8 x i16> @umull_noextvec_v8i8_v8i16(<8 x i8> %arg) nounwind {
10901090
; Do not use SMULL if the BUILD_VECTOR element values are too big.
1091-
; CHECK-LABEL: umull_noextvec_v8i8_v8i16:
1092-
; CHECK: // %bb.0:
1093-
; CHECK-NEXT: mov w8, #999 // =0x3e7
1094-
; CHECK-NEXT: ushll v0.8h, v0.8b, #0
1095-
; CHECK-NEXT: dup v1.8h, w8
1096-
; CHECK-NEXT: mul v0.8h, v0.8h, v1.8h
1097-
; CHECK-NEXT: ret
1091+
; CHECK-NEON-LABEL: umull_noextvec_v8i8_v8i16:
1092+
; CHECK-NEON: // %bb.0:
1093+
; CHECK-NEON-NEXT: mov w8, #999 // =0x3e7
1094+
; CHECK-NEON-NEXT: ushll v0.8h, v0.8b, #0
1095+
; CHECK-NEON-NEXT: dup v1.8h, w8
1096+
; CHECK-NEON-NEXT: mul v0.8h, v0.8h, v1.8h
1097+
; CHECK-NEON-NEXT: ret
1098+
;
1099+
; CHECK-SVE-LABEL: umull_noextvec_v8i8_v8i16:
1100+
; CHECK-SVE: // %bb.0:
1101+
; CHECK-SVE-NEXT: mov w8, #999 // =0x3e7
1102+
; CHECK-SVE-NEXT: ushll v0.8h, v0.8b, #0
1103+
; CHECK-SVE-NEXT: dup v1.8h, w8
1104+
; CHECK-SVE-NEXT: mul v0.8h, v0.8h, v1.8h
1105+
; CHECK-SVE-NEXT: ret
1106+
;
1107+
; CHECK-GI-LABEL: umull_noextvec_v8i8_v8i16:
1108+
; CHECK-GI: // %bb.0:
1109+
; CHECK-GI-NEXT: adrp x8, .LCPI38_0
1110+
; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0
1111+
; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI38_0]
1112+
; CHECK-GI-NEXT: mul v0.8h, v0.8h, v1.8h
1113+
; CHECK-GI-NEXT: ret
10981114
%tmp3 = zext <8 x i8> %arg to <8 x i16>
10991115
%tmp4 = mul <8 x i16> %tmp3, <i16 999, i16 999, i16 999, i16 999, i16 999, i16 999, i16 999, i16 999>
11001116
ret <8 x i16> %tmp4

‎llvm/test/CodeGen/AArch64/neon-mov.ll

Lines changed: 60 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -109,11 +109,29 @@ define <4 x i32> @movi4s_lsl16() {
109109
}
110110

111111
define <4 x i32> @movi4s_fneg() {
112-
; CHECK-LABEL: movi4s_fneg:
113-
; CHECK: // %bb.0:
114-
; CHECK-NEXT: movi v0.4s, #240, lsl #8
115-
; CHECK-NEXT: fneg v0.4s, v0.4s
116-
; CHECK-NEXT: ret
112+
; CHECK-NOFP16-SD-LABEL: movi4s_fneg:
113+
; CHECK-NOFP16-SD: // %bb.0:
114+
; CHECK-NOFP16-SD-NEXT: movi v0.4s, #240, lsl #8
115+
; CHECK-NOFP16-SD-NEXT: fneg v0.4s, v0.4s
116+
; CHECK-NOFP16-SD-NEXT: ret
117+
;
118+
; CHECK-FP16-SD-LABEL: movi4s_fneg:
119+
; CHECK-FP16-SD: // %bb.0:
120+
; CHECK-FP16-SD-NEXT: movi v0.4s, #240, lsl #8
121+
; CHECK-FP16-SD-NEXT: fneg v0.4s, v0.4s
122+
; CHECK-FP16-SD-NEXT: ret
123+
;
124+
; CHECK-NOFP16-GI-LABEL: movi4s_fneg:
125+
; CHECK-NOFP16-GI: // %bb.0:
126+
; CHECK-NOFP16-GI-NEXT: movi v0.4s, #240, lsl #8
127+
; CHECK-NOFP16-GI-NEXT: fneg v0.4s, v0.4s
128+
; CHECK-NOFP16-GI-NEXT: ret
129+
;
130+
; CHECK-FP16-GI-LABEL: movi4s_fneg:
131+
; CHECK-FP16-GI: // %bb.0:
132+
; CHECK-FP16-GI-NEXT: movi v0.4s, #240, lsl #8
133+
; CHECK-FP16-GI-NEXT: fneg v0.4s, v0.4s
134+
; CHECK-FP16-GI-NEXT: ret
117135
ret <4 x i32> <i32 2147545088, i32 2147545088, i32 2147545088, i32 2147545088>
118136
}
119137

@@ -290,17 +308,23 @@ define <8 x i16> @mvni8h_neg() {
290308
; CHECK-NOFP16-SD-NEXT: dup v0.8h, w8
291309
; CHECK-NOFP16-SD-NEXT: ret
292310
;
293-
; CHECK-FP16-LABEL: mvni8h_neg:
294-
; CHECK-FP16: // %bb.0:
295-
; CHECK-FP16-NEXT: movi v0.8h, #240
296-
; CHECK-FP16-NEXT: fneg v0.8h, v0.8h
297-
; CHECK-FP16-NEXT: ret
311+
; CHECK-FP16-SD-LABEL: mvni8h_neg:
312+
; CHECK-FP16-SD: // %bb.0:
313+
; CHECK-FP16-SD-NEXT: movi v0.8h, #240
314+
; CHECK-FP16-SD-NEXT: fneg v0.8h, v0.8h
315+
; CHECK-FP16-SD-NEXT: ret
298316
;
299317
; CHECK-NOFP16-GI-LABEL: mvni8h_neg:
300318
; CHECK-NOFP16-GI: // %bb.0:
301-
; CHECK-NOFP16-GI-NEXT: mov w8, #-32528 // =0xffff80f0
302-
; CHECK-NOFP16-GI-NEXT: dup v0.8h, w8
319+
; CHECK-NOFP16-GI-NEXT: adrp x8, .LCPI32_0
320+
; CHECK-NOFP16-GI-NEXT: ldr q0, [x8, :lo12:.LCPI32_0]
303321
; CHECK-NOFP16-GI-NEXT: ret
322+
;
323+
; CHECK-FP16-GI-LABEL: mvni8h_neg:
324+
; CHECK-FP16-GI: // %bb.0:
325+
; CHECK-FP16-GI-NEXT: movi v0.8h, #240
326+
; CHECK-FP16-GI-NEXT: fneg v0.8h, v0.8h
327+
; CHECK-FP16-GI-NEXT: ret
304328
ret <8 x i16> <i16 33008, i16 33008, i16 33008, i16 33008, i16 33008, i16 33008, i16 33008, i16 33008>
305329
}
306330

@@ -470,11 +494,29 @@ define <2 x double> @fmov2d() {
470494
}
471495

472496
define <2 x double> @fmov2d_neg0() {
473-
; CHECK-LABEL: fmov2d_neg0:
474-
; CHECK: // %bb.0:
475-
; CHECK-NEXT: movi v0.2d, #0000000000000000
476-
; CHECK-NEXT: fneg v0.2d, v0.2d
477-
; CHECK-NEXT: ret
497+
; CHECK-NOFP16-SD-LABEL: fmov2d_neg0:
498+
; CHECK-NOFP16-SD: // %bb.0:
499+
; CHECK-NOFP16-SD-NEXT: movi v0.2d, #0000000000000000
500+
; CHECK-NOFP16-SD-NEXT: fneg v0.2d, v0.2d
501+
; CHECK-NOFP16-SD-NEXT: ret
502+
;
503+
; CHECK-FP16-SD-LABEL: fmov2d_neg0:
504+
; CHECK-FP16-SD: // %bb.0:
505+
; CHECK-FP16-SD-NEXT: movi v0.2d, #0000000000000000
506+
; CHECK-FP16-SD-NEXT: fneg v0.2d, v0.2d
507+
; CHECK-FP16-SD-NEXT: ret
508+
;
509+
; CHECK-NOFP16-GI-LABEL: fmov2d_neg0:
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; CHECK-NOFP16-GI: // %bb.0:
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; CHECK-NOFP16-GI-NEXT: movi v0.2d, #0000000000000000
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; CHECK-NOFP16-GI-NEXT: fneg v0.2d, v0.2d
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; CHECK-NOFP16-GI-NEXT: ret
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;
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; CHECK-FP16-GI-LABEL: fmov2d_neg0:
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; CHECK-FP16-GI: // %bb.0:
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; CHECK-FP16-GI-NEXT: movi v0.2d, #0000000000000000
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; CHECK-FP16-GI-NEXT: fneg v0.2d, v0.2d
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; CHECK-FP16-GI-NEXT: ret
478520
ret <2 x double> <double -0.0, double -0.0>
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}
480522

@@ -539,4 +581,5 @@ define <2 x i32> @movi1d() {
539581
ret <2 x i32> %1
540582
}
541583
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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; CHECK-FP16: {{.*}}
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; CHECK-NOFP16: {{.*}}

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