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#define DEBUG_TYPE " riscv-isel"
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using namespace llvm ;
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+ using namespace MIPatternMatch ;
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#define GET_GLOBALISEL_PREDICATE_BITSET
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#include " RISCVGenGlobalISel.inc"
@@ -536,14 +537,12 @@ void RISCVInstructionSelector::getICMPOperandsForBranch(
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RHS = MI.getOperand (3 ).getReg ();
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// Adjust comparisons to use comparison with 0 if possible.
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- MachineInstr *MaybeConstant = MRI.getVRegDef (RHS);
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- if (MaybeConstant && MaybeConstant->getOpcode () == TargetOpcode::G_CONSTANT) {
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+ if (auto Constant = matchConstant<int64_t >(RHS, MRI)) {
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switch (ICMPCC) {
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case CmpInst::Predicate::ICMP_SGT:
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// Convert X > -1 to X >= 0
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- if (MaybeConstant->getOperand (1 ).getCImm ()->getSExtValue () == -1 ) {
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- MachineInstr *Zero = MIB.buildConstant (
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- MRI.getType (MaybeConstant->getOperand (0 ).getReg ()), 0 );
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+ if (*Constant == -1 ) {
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+ MachineInstr *Zero = MIB.buildConstant (MRI.getType (RHS), 0 );
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selectConstant (*Zero, MIB, MRI);
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CC = RISCVCC::COND_GE;
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RHS = Zero->getOperand (0 ).getReg ();
@@ -552,9 +551,8 @@ void RISCVInstructionSelector::getICMPOperandsForBranch(
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break ;
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case CmpInst::Predicate::ICMP_SLT:
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// Convert X < 1 to 0 >= X
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- if (MaybeConstant->getOperand (1 ).getCImm ()->getSExtValue () == 1 ) {
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- MachineInstr *Zero = MIB.buildConstant (
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- MRI.getType (MaybeConstant->getOperand (0 ).getReg ()), 0 );
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+ if (*Constant == 1 ) {
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+ MachineInstr *Zero = MIB.buildConstant (MRI.getType (RHS), 0 );
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selectConstant (*Zero, MIB, MRI);
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CC = RISCVCC::COND_GE;
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RHS = LHS;
@@ -598,12 +596,12 @@ bool RISCVInstructionSelector::selectSelect(MachineInstr &MI,
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// If MI is a G_SELECT(G_ICMP(tst, A, B), C, D) then we can use (A, B, tst)
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// as the (LHS, RHS, CC) of the Select_GPR_Using_CC_GPR.
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- MachineInstr *MaybeICMP = MRI. getVRegDef ( MI.getOperand (1 ).getReg () );
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- bool Op1IsICMP = MaybeICMP && MaybeICMP-> getOpcode () == TargetOpcode::G_ICMP ;
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+ Register MIOp1Reg = MI.getOperand (1 ).getReg ();
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+ bool Op1IsICMP = mi_match (MIOp1Reg, MRI, m_GICmp ( m_Pred (), m_Reg (), m_Reg ())) ;
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RISCVCC::CondCode CC;
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Register LHS, RHS;
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if (Op1IsICMP)
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- getICMPOperandsForBranch (*MaybeICMP , MIB, MRI, CC, LHS, RHS);
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+ getICMPOperandsForBranch (*MRI. getVRegDef (MIOp1Reg) , MIB, MRI, CC, LHS, RHS);
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Register Op1 = Op1IsICMP ? LHS : MI.getOperand (1 ).getReg ();
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Register Op2 = Op1IsICMP ? RHS : RISCV::X0;
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