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[RISCV][MC] MC layer support for the experimental zalasr extension
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‎clang/test/Preprocessor/riscv-target-features.c

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@@ -144,6 +144,7 @@
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// CHECK-NOT: __riscv_zaamo {{.*$}}
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// CHECK-NOT: __riscv_zacas {{.*$}}
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// CHECK-NOT: __riscv_zalasr {{.*$}}
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// CHECK-NOT: __riscv_zalrsc {{.*$}}
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// CHECK-NOT: __riscv_zcmop {{.*$}}
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// CHECK-NOT: __riscv_zfbfmin {{.*$}}
@@ -1333,6 +1334,14 @@
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZACAS-EXT %s
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// CHECK-ZACAS-EXT: __riscv_zacas 1000000{{$}}
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// RUN: %clang --target=riscv32 -menable-experimental-extensions \
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// RUN: -march=rv32i_zalasr0p1 -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZALASR-EXT %s
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// RUN: %clang --target=riscv64 -menable-experimental-extensions \
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// RUN: -march=rv64i_zalasr0p1 -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZALASR-EXT %s
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// CHECK-ZALASR-EXT: __riscv_zalasr 1000{{$}}
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// RUN: %clang --target=riscv32 -menable-experimental-extensions \
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// RUN: -march=rv32i_zalrsc0p2 -E -dM %s \
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// RUN: -o - | FileCheck --check-prefix=CHECK-ZALRSC-EXT %s

‎llvm/docs/RISCVUsage.rst

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@@ -229,6 +229,9 @@ The primary goal of experimental support is to assist in the process of ratifica
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``experimental-zacas``
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LLVM implements the `1.0-rc1 draft specification <https://github.com/riscv/riscv-zacas/releases/tag/v1.0-rc1>`_.
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``experimental-zalasr``
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LLVM implements the `0.0.5 draft specification <https://github.com/mehnadnerd/riscv-zalasr>`_.
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``experimental-zfbfmin``, ``experimental-zvfbfmin``, ``experimental-zvfbfwma``
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LLVM implements assembler support for the `1.0.0-rc2 specification <https://github.com/riscv/riscv-bfloat16/releases/tag/v59042fc71c31a9bcb2f1957621c960ed36fac401>`_.
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‎llvm/lib/Support/RISCVISAInfo.cpp

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@@ -196,6 +196,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
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static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
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{"zaamo", {0, 2}},
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{"zacas", {1, 0}},
199+
{"zalasr", {0, 1}},
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{"zalrsc", {0, 2}},
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{"zcmop", {0, 2}},

‎llvm/lib/Target/RISCV/RISCVFeatures.td

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@@ -797,6 +797,13 @@ def FeatureStdExtSvpbmt
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: SubtargetFeature<"svpbmt", "HasStdExtSvpbmt", "true",
798798
"'Svpbmt' (Page-Based Memory Types)">;
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def FeatureStdExtZalasr
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: SubtargetFeature<"experimental-zalasr", "HasStdExtZalasr", "true",
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"'Zalasr' (Load-Acquire and Store-Release Instructions)">;
803+
def HasStdExtZalasr : Predicate<"Subtarget->hasStdExtZalasr()">,
804+
AssemblerPredicate<(all_of FeatureStdExtZalasr),
805+
"'Zalasr' (Load-Acquire and Store-Release Instructions)">;
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//===----------------------------------------------------------------------===//
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// Vendor extensions
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//===----------------------------------------------------------------------===//

‎llvm/lib/Target/RISCV/RISCVInstrInfo.td

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@@ -2144,6 +2144,7 @@ include "RISCVInstrInfoM.td"
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// Atomic
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include "RISCVInstrInfoA.td"
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include "RISCVInstrInfoZa.td"
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include "RISCVInstrInfoZalasr.td"
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// Scalar FP
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include "RISCVInstrInfoF.td"

‎llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td

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//===-- RISCVInstrInfoZalasr.td - RISC-V 'Zalasr' instructions -------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the RISC-V instructions from the Zalasr (Load-Acquire
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// and Store-Release) extension
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction class templates
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//===----------------------------------------------------------------------===//
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let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
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class LAQ_r<bit aq, bit rl, bits<3> funct3, string opcodestr>
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: RVInstRAtomic<0b00110, aq, rl, funct3, OPC_AMO,
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(outs GPR:$rd), (ins GPRMemZeroOffset:$rs1),
22+
opcodestr, "$rd, $rs1"> {
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let rs2 = 0;
24+
}
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let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
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class SRL_r<bit aq, bit rl, bits<3> funct3, string opcodestr>
28+
: RVInstRAtomic<0b00111, aq, rl, funct3, OPC_AMO,
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(outs ), (ins GPRMemZeroOffset:$rs1, GPR:$rs2),
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opcodestr, "$rs2, $rs1"> {
31+
let rd = 0;
32+
}
33+
multiclass LAQ_r_aq_rl<bits<3> funct3, string opcodestr> {
34+
def _AQ : LAQ_r<1, 0, funct3, opcodestr # ".aq">;
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def _AQ_RL : LAQ_r<1, 1, funct3, opcodestr # ".aqrl">;
36+
}
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multiclass SRL_r_aq_rl<bits<3> funct3, string opcodestr> {
39+
def _RL : SRL_r<0, 1, funct3, opcodestr # ".rl">;
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def _AQ_RL : SRL_r<1, 1, funct3, opcodestr # ".aqrl">;
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}
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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let Predicates = [HasStdExtZalasr] in {
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defm LB : LAQ_r_aq_rl<0b000, "lb">;
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defm LH : LAQ_r_aq_rl<0b001, "lh">;
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defm LW : LAQ_r_aq_rl<0b010, "lw">;
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defm SB : SRL_r_aq_rl<0b000, "sb">;
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defm SH : SRL_r_aq_rl<0b001, "sh">;
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defm SW : SRL_r_aq_rl<0b010, "sw">;
55+
} // Predicates = [HasStdExtZalasr]
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57+
let Predicates = [HasStdExtZalasr, IsRV64] in {
58+
defm LD : LAQ_r_aq_rl<0b011, "ld">;
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defm SD : SRL_r_aq_rl<0b011, "sd">;
60+
} // Predicates = [HasStdExtZalasr, IsRV64]
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//===----------------------------------------------------------------------===//
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// Pseudo-instructions and codegen patterns
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//===----------------------------------------------------------------------===//
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// Future work: Work out mapping with leading/trailing fences, &c

‎llvm/test/CodeGen/RISCV/attributes.ll

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@@ -97,6 +97,7 @@
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zacas %s -o - | FileCheck --check-prefix=RV32ZACAS %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zalrsc %s -o - | FileCheck --check-prefix=RV32ZALRSC %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicfilp %s -o - | FileCheck --check-prefix=RV32ZICFILP %s
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-zalasr %s -o - | FileCheck --check-prefix=RV32ZALASR %s
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; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s
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; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s
@@ -201,6 +202,7 @@
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zacas %s -o - | FileCheck --check-prefix=RV64ZACAS %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zalrsc %s -o - | FileCheck --check-prefix=RV64ZALRSC %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicfilp %s -o - | FileCheck --check-prefix=RV64ZICFILP %s
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; RUN: llc -mtriple=riscv64 -mattr=+experimental-zalasr %s -o - | FileCheck --check-prefix=RV64ZALASR %s
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; CHECK: .attribute 4, 16
206208

@@ -298,6 +300,7 @@
298300
; RV32ZVFBFWMA: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0"
299301
; RV32ZAAMO: .attribute 5, "rv32i2p1_zaamo0p2"
300302
; RV32ZACAS: .attribute 5, "rv32i2p1_a2p1_zacas1p0"
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; RV32ZALASR: .attribute 5, "rv32i2p1_zalasr0p1"
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; RV32ZALRSC: .attribute 5, "rv32i2p1_zalrsc0p2"
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; RV32ZICFILP: .attribute 5, "rv32i2p1_zicfilp0p4"
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@@ -401,6 +404,7 @@
401404
; RV64ZVFBFWMA: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0"
402405
; RV64ZAAMO: .attribute 5, "rv64i2p1_zaamo0p2"
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; RV64ZACAS: .attribute 5, "rv64i2p1_a2p1_zacas1p0"
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; RV64ZALASR: .attribute 5, "rv64i2p1_zalasr0p1"
404408
; RV64ZALRSC: .attribute 5, "rv64i2p1_zalrsc0p2"
405409
; RV64ZICFILP: .attribute 5, "rv64i2p1_zicfilp0p4"
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‎llvm/test/MC/RISCV/attribute-arch.s

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@@ -309,6 +309,9 @@
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.attribute arch, "rv32izacas1p0"
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# CHECK: attribute 5, "rv32i2p1_a2p1_zacas1p0"
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312+
.attribute arch, "rv32izalasr0p1"
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# CHECK: attribute 5, "rv32i2p1_zalasr0p1"
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312315
.attribute arch, "rv32i_xcvalu"
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# CHECK: attribute 5, "rv32i2p1_xcvalu1p0"
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‎llvm/test/MC/RISCV/rv32zalasr-invalid.s

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# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zalasr < %s 2>&1 | FileCheck -check-prefixes=CHECK %s
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# CHECK: error: instruction requires the following: RV64I Base Instruction Set{{$}}
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ld.aq a1, (t0)
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# CHECK: error: instruction requires the following: RV64I Base Instruction Set{{$}}
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ld.aqrl a1, (t0)
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# CHECK: error: instruction requires the following: RV64I Base Instruction Set{{$}}
10+
sd.rl a1, (t0)
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# CHECK: error: instruction requires the following: RV64I Base Instruction Set{{$}}
13+
sd.aqrl a1, (t0)
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# CHECK: error: unrecognized instruction mnemonic
16+
lw. a1, (t0)
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18+
# CHECK: error: unrecognized instruction mnemonic
19+
lw.rl t3, 0(t5)
20+
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# CHECK: error: unrecognized instruction mnemonic
22+
lh.rlaq t4, (t6)
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# CHECK: error: unrecognized instruction mnemonic
25+
sb. a1, (t0)
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27+
# CHECK: error: unrecognized instruction mnemonic
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sh.aq t3, 0(t5)
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# CHECK: error: unrecognized instruction mnemonic
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sh.rlaq t4, (t6)
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# CHECK: error: optional integer offset must be 0
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lw.aq zero, 1(a0)
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36+
# CHECK: error: optional integer offset must be 0
37+
sw.rl t1, 2(s0)
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# CHECK: error: optional integer offset must be 0
40+
sb.aqrl sp, 3(s2)

‎llvm/test/MC/RISCV/rv32zalasr-valid.s

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# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zalasr -riscv-no-aliases -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
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# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zalasr < %s \
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# RUN: | llvm-objdump --mattr=+experimental-zalasr -M no-aliases -d -r - \
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# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
6+
# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zalasr -riscv-no-aliases -show-encoding \
7+
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
8+
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zalasr < %s \
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# RUN: | llvm-objdump --mattr=+experimental-zalasr -M no-aliases -d -r - \
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# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
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#
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# RUN: not llvm-mc -triple riscv32 \
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# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
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# RUN: | FileCheck --check-prefixes=CHECK-NO-EXT %s
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# RUN: not llvm-mc -triple riscv64 \
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# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
17+
# RUN: | FileCheck --check-prefixes=CHECK-NO-EXT %s
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19+
# CHECK-ASM-AND-OBJ: lb.aq t1, (a0)
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# CHECK-ASM: encoding: [0x2f,0x03,0x05,0x34]
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# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
22+
lb.aq t1, 0(a0)
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24+
# CHECK-ASM-AND-OBJ: lh.aq t1, (a0)
25+
# CHECK-ASM: encoding: [0x2f,0x13,0x05,0x34]
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# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
27+
lh.aq t1, 0(a0)
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# CHECK-ASM-AND-OBJ: lw.aq t1, (a0)
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# CHECK-ASM: encoding: [0x2f,0x23,0x05,0x34]
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# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
32+
lw.aq t1, (a0)
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# CHECK-ASM-AND-OBJ: lb.aqrl t1, (a0)
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# CHECK-ASM: encoding: [0x2f,0x03,0x05,0x36]
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# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
37+
lb.aqrl t1, 0(a0)
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39+
# CHECK-ASM-AND-OBJ: lh.aqrl t1, (a0)
40+
# CHECK-ASM: encoding: [0x2f,0x13,0x05,0x36]
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# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
42+
lh.aqrl t1, (a0)
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44+
# CHECK-ASM-AND-OBJ: lw.aqrl t1, (a0)
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# CHECK-ASM: encoding: [0x2f,0x23,0x05,0x36]
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# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
47+
lw.aqrl t1, (a0)
48+
49+
50+
# CHECK-ASM-AND-OBJ: sb.rl t1, (a0)
51+
# CHECK-ASM: encoding: [0x2f,0x00,0x65,0x3a]
52+
# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
53+
sb.rl t1, (a0)
54+
55+
# CHECK-ASM-AND-OBJ: sh.rl t1, (a0)
56+
# CHECK-ASM: encoding: [0x2f,0x10,0x65,0x3a]
57+
# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
58+
sh.rl t1, 0(a0)
59+
60+
# CHECK-ASM-AND-OBJ: sw.rl t1, (a0)
61+
# CHECK-ASM: encoding: [0x2f,0x20,0x65,0x3a]
62+
# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
63+
sw.rl t1, (a0)
64+
65+
# CHECK-ASM-AND-OBJ: sb.aqrl t1, (a0)
66+
# CHECK-ASM: encoding: [0x2f,0x00,0x65,0x3e]
67+
# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
68+
sb.aqrl t1, (a0)
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70+
# CHECK-ASM-AND-OBJ: sh.aqrl t1, (a0)
71+
# CHECK-ASM: encoding: [0x2f,0x10,0x65,0x3e]
72+
# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
73+
sh.aqrl t1, 0(a0)
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75+
# CHECK-ASM-AND-OBJ: sw.aqrl t1, (a0)
76+
# CHECK-ASM: encoding: [0x2f,0x20,0x65,0x3e]
77+
# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
78+
sw.aqrl t1, 0(a0)

‎llvm/test/MC/RISCV/rv64zalasr-invalid.s

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@@ -0,0 +1,28 @@
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# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zalasr < %s 2>&1 | FileCheck -check-prefixes=CHECK %s
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3+
# CHECK: error: unrecognized instruction mnemonic
4+
lw. a1, (t0)
5+
6+
# CHECK: error: unrecognized instruction mnemonic
7+
lw.rl t3, 0(t5)
8+
9+
# CHECK: error: unrecognized instruction mnemonic
10+
lh.rlaq t4, (t6)
11+
12+
# CHECK: error: unrecognized instruction mnemonic
13+
sb. a1, (t0)
14+
15+
# CHECK: error: unrecognized instruction mnemonic
16+
sh.aq t3, 0(t5)
17+
18+
# CHECK: error: unrecognized instruction mnemonic
19+
sh.rlaq t4, (t6)
20+
21+
# CHECK: error: optional integer offset must be 0
22+
lw.aq zero, 1(a0)
23+
24+
# CHECK: error: optional integer offset must be 0
25+
sw.rl t1, 2(s0)
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# CHECK: error: optional integer offset must be 0
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sb.aqrl sp, 3(s2)

‎llvm/test/MC/RISCV/rv64zalasr-valid.s

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# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zalasr -riscv-no-aliases -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
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# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zalasr < %s \
4+
# RUN: | llvm-objdump --mattr=+experimental-zalasr -M no-aliases -d -r - \
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# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
6+
#
7+
# RUN: not llvm-mc -triple riscv64 \
8+
# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \
9+
# RUN: | FileCheck --check-prefixes=CHECK-NO-EXT %s
10+
11+
12+
# CHECK-ASM-AND-OBJ: ld.aq t1, (a0)
13+
# CHECK-ASM: encoding: [0x2f,0x33,0x05,0x34]
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# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
15+
ld.aq t1, (a0)
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# CHECK-ASM-AND-OBJ: ld.aqrl t1, (a0)
18+
# CHECK-ASM: encoding: [0x2f,0x33,0x05,0x36]
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# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
20+
ld.aqrl t1, 0(a0)
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22+
23+
# CHECK-ASM-AND-OBJ: sd.rl t1, (a0)
24+
# CHECK-ASM: encoding: [0x2f,0x30,0x65,0x3a]
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# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
26+
sd.rl t1, 0(a0)
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28+
# CHECK-ASM-AND-OBJ: sd.aqrl t1, (a0)
29+
# CHECK-ASM: encoding: [0x2f,0x30,0x65,0x3e]
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# CHECK-NO-EXT: error: instruction requires the following: 'Zalasr' (Load-Acquire and Store-Release Instructions){{$}}
31+
sd.aqrl t1, (a0)

‎llvm/unittests/Support/RISCVISAInfoTest.cpp

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@@ -856,6 +856,7 @@ Experimental extensions
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zimop 0.1
857857
zaamo 0.2
858858
zacas 1.0
859+
zalasr 0.1
859860
zalrsc 0.2
860861
zfbfmin 1.0
861862
zcmop 0.2

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