@@ -342,6 +342,7 @@ bool MipsExpandPseudo::expandAtomicBinOpSubword(
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bool IsMin = false ;
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bool IsMax = false ;
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bool IsUnsigned = false ;
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+ bool DestOK = false ;
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unsigned Opcode = 0 ;
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switch (I->getOpcode ()) {
@@ -388,6 +389,7 @@ bool MipsExpandPseudo::expandAtomicBinOpSubword(
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Opcode = Mips::XOR;
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break ;
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case Mips::ATOMIC_LOAD_UMIN_I8_POSTRA:
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+ SEOp = Mips::SEB;
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IsUnsigned = true ;
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IsMin = true ;
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break ;
@@ -403,6 +405,7 @@ bool MipsExpandPseudo::expandAtomicBinOpSubword(
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IsMin = true ;
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break ;
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case Mips::ATOMIC_LOAD_UMAX_I8_POSTRA:
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+ SEOp = Mips::SEB;
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IsUnsigned = true ;
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IsMax = true ;
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break ;
@@ -473,48 +476,36 @@ bool MipsExpandPseudo::expandAtomicBinOpSubword(
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unsigned SELOldVal = IsMax ? SELEQZ : SELNEZ;
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unsigned MOVIncr = IsMax ? MOVN : MOVZ;
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- // For little endian we need to clear uninterested bits.
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- if (STI->isLittle ()) {
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- if (!IsUnsigned) {
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- BuildMI (loopMBB, DL, TII->get (Mips::SRAV), OldVal)
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- .addReg (OldVal)
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- .addReg (ShiftAmnt);
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- BuildMI (loopMBB, DL, TII->get (Mips::SRAV), Incr)
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- .addReg (Incr)
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- .addReg (ShiftAmnt);
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- if (STI->hasMips32r2 ()) {
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- BuildMI (loopMBB, DL, TII->get (SEOp), OldVal).addReg (OldVal);
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- BuildMI (loopMBB, DL, TII->get (SEOp), Incr).addReg (Incr);
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- } else {
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- const unsigned ShiftImm = SEOp == Mips::SEH ? 16 : 24 ;
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- BuildMI (loopMBB, DL, TII->get (Mips::SLL), OldVal)
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- .addReg (OldVal, RegState::Kill)
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- .addImm (ShiftImm);
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- BuildMI (loopMBB, DL, TII->get (Mips::SRA), OldVal)
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- .addReg (OldVal, RegState::Kill)
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- .addImm (ShiftImm);
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- BuildMI (loopMBB, DL, TII->get (Mips::SLL), Incr)
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- .addReg (Incr, RegState::Kill)
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- .addImm (ShiftImm);
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- BuildMI (loopMBB, DL, TII->get (Mips::SRA), Incr)
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- .addReg (Incr, RegState::Kill)
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- .addImm (ShiftImm);
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- }
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- } else {
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- // and OldVal, OldVal, Mask
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- // and Incr, Incr, Mask
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- BuildMI (loopMBB, DL, TII->get (Mips::AND), OldVal)
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- .addReg (OldVal)
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- .addReg (Mask);
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- BuildMI (loopMBB, DL, TII->get (Mips::AND), Incr)
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- .addReg (Incr)
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- .addReg (Mask);
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- }
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+ BuildMI (loopMBB, DL, TII->get (Mips::SRAV), StoreVal)
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+ .addReg (OldVal)
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+ .addReg (ShiftAmnt);
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+ if (STI->hasMips32r2 () && !IsUnsigned) {
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+ BuildMI (loopMBB, DL, TII->get (SEOp), StoreVal).addReg (StoreVal);
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+ } else if (STI->hasMips32r2 () && IsUnsigned) {
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+ const unsigned OpMask = SEOp == Mips::SEH ? 0xffff : 0xff ;
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+ BuildMI (loopMBB, DL, TII->get (Mips::ANDi), StoreVal).addReg (StoreVal).addImm (OpMask);
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+ } else {
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+ const unsigned ShiftImm = SEOp == Mips::SEH ? 16 : 24 ;
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+ const unsigned SROp = IsUnsigned ? Mips::SRL : Mips::SRA;
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+ BuildMI (loopMBB, DL, TII->get (Mips::SLL), StoreVal)
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+ .addReg (StoreVal, RegState::Kill)
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+ .addImm (ShiftImm);
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+ BuildMI (loopMBB, DL, TII->get (SROp), StoreVal)
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+ .addReg (StoreVal, RegState::Kill)
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+ .addImm (ShiftImm);
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}
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- // unsigned: sltu Scratch4, oldVal, Incr
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- // signed: slt Scratch4, oldVal, Incr
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+ BuildMI (loopMBB, DL, TII->get (Mips::OR), Dest)
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+ .addReg (Mips::ZERO)
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+ .addReg (StoreVal);
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+ DestOK = true ;
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+ BuildMI (loopMBB, DL, TII->get (Mips::SLLV), StoreVal)
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+ .addReg (StoreVal)
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+ .addReg (ShiftAmnt);
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+
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+ // unsigned: sltu Scratch4, StoreVal, Incr
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+ // signed: slt Scratch4, StoreVal, Incr
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BuildMI (loopMBB, DL, TII->get (SLTScratch4), Scratch4)
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- .addReg (OldVal )
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+ .addReg (StoreVal )
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.addReg (Incr);
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if (STI->hasMips64r6 () || STI->hasMips32r6 ()) {
@@ -525,7 +516,7 @@ bool MipsExpandPseudo::expandAtomicBinOpSubword(
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// seleqz Scratch4, Incr, Scratch4
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// or BinOpRes, BinOpRes, Scratch4
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BuildMI (loopMBB, DL, TII->get (SELOldVal), BinOpRes)
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- .addReg (OldVal )
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+ .addReg (StoreVal )
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.addReg (Scratch4);
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BuildMI (loopMBB, DL, TII->get (SELIncr), Scratch4)
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.addReg (Incr)
@@ -534,12 +525,12 @@ bool MipsExpandPseudo::expandAtomicBinOpSubword(
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.addReg (BinOpRes)
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.addReg (Scratch4);
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} else {
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- // max: move BinOpRes, OldVal
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+ // max: move BinOpRes, StoreVal
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// movn BinOpRes, Incr, Scratch4, BinOpRes
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- // min: move BinOpRes, OldVal
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+ // min: move BinOpRes, StoreVal
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// movz BinOpRes, Incr, Scratch4, BinOpRes
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BuildMI (loopMBB, DL, TII->get (OR), BinOpRes)
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- .addReg (OldVal )
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+ .addReg (StoreVal )
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.addReg (Mips::ZERO);
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BuildMI (loopMBB, DL, TII->get (MOVIncr), BinOpRes)
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.addReg (Incr)
@@ -586,23 +577,24 @@ bool MipsExpandPseudo::expandAtomicBinOpSubword(
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// srl srlres,maskedoldval1,shiftamt
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// sign_extend dest,srlres
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- sinkMBB-> addSuccessor (exitMBB, BranchProbability::getOne ());
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-
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- BuildMI (sinkMBB, DL, TII->get (Mips::AND), Dest)
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- . addReg (OldVal). addReg (Mask);
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- BuildMI (sinkMBB, DL, TII-> get (Mips::SRLV), Dest)
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- . addReg (Dest) .addReg (ShiftAmnt);
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+ if (!DestOK) {
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+ sinkMBB-> addSuccessor (exitMBB, BranchProbability::getOne ());
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+ BuildMI (sinkMBB, DL, TII->get (Mips::AND), Dest). addReg (OldVal). addReg (Mask);
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+ BuildMI (sinkMBB, DL, TII-> get (Mips::SRLV), Dest)
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+ . addReg ( Dest)
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+ .addReg (ShiftAmnt);
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- if (STI->hasMips32r2 ()) {
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- BuildMI (sinkMBB, DL, TII->get (SEOp), Dest).addReg (Dest);
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- } else {
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- const unsigned ShiftImm = SEOp == Mips::SEH ? 16 : 24 ;
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- BuildMI (sinkMBB, DL, TII->get (Mips::SLL), Dest)
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- .addReg (Dest, RegState::Kill)
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- .addImm (ShiftImm);
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- BuildMI (sinkMBB, DL, TII->get (Mips::SRA), Dest)
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- .addReg (Dest, RegState::Kill)
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- .addImm (ShiftImm);
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+ if (STI->hasMips32r2 ()) {
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+ BuildMI (sinkMBB, DL, TII->get (SEOp), Dest).addReg (Dest);
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+ } else {
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+ const unsigned ShiftImm = SEOp == Mips::SEH ? 16 : 24 ;
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+ BuildMI (sinkMBB, DL, TII->get (Mips::SLL), Dest)
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+ .addReg (Dest, RegState::Kill)
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+ .addImm (ShiftImm);
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+ BuildMI (sinkMBB, DL, TII->get (Mips::SRA), Dest)
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+ .addReg (Dest, RegState::Kill)
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+ .addImm (ShiftImm);
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+ }
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}
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LivePhysRegs LiveRegs;
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