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llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2008,9 +2008,10 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
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// S64 is only legal on SALU, and needs to be broken into 32-bit elements in
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// RegBankSelect.
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auto &SextInReg = getActionDefinitionsBuilder(G_SEXT_INREG)
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.legalFor({{S32}, {S64}})
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.widenScalarIf(typeIs(0, S16), widenScalarOrEltToNextPow2(0, 32));
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auto &SextInReg =
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getActionDefinitionsBuilder(G_SEXT_INREG)
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.legalFor({{S32}, {S64}})
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.widenScalarIf(typeIs(0, S16), widenScalarOrEltToNextPow2(0, 32));
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if (ST.hasVOP3PInsts()) {
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SextInReg.lowerFor({{V2S16}})

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