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[RISCV] Add XTheadMac patterns for -riscv-experimental-rv64-legal-i32.
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‎llvm/lib/Target/RISCV/RISCVInstrInfo.td

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@@ -1186,6 +1186,7 @@ def assertsexti32 : PatFrag<(ops node:$src), (assertsext node:$src), [{
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return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLE(MVT::i32);
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}]>;
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def sexti16 : ComplexPattern<XLenVT, 1, "selectSExtBits<16>">;
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def sexti16i32 : ComplexPattern<i32, 1, "selectSExtBits<16>">;
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def sexti32 : ComplexPattern<i64, 1, "selectSExtBits<32>">;
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def assertzexti32 : PatFrag<(ops node:$src), (assertzext node:$src), [{
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return cast<VTSDNode>(N->getOperand(1))->getVT().bitsLE(MVT::i32);

‎llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td

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@@ -935,3 +935,20 @@ def : Pat<(select (riscv_seteq (XLenVT GPR:$cond)), (i32 0), (i32 GPR:$b)),
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def : Pat<(select (riscv_setne (XLenVT GPR:$cond)), (i32 0), (i32 GPR:$b)),
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(TH_MVNEZ GPR:$b, (XLenVT X0), GPR:$cond)>;
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} // Predicates = [HasVendorXTHeadCondMov]
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let Predicates = [HasVendorXTHeadMac, IsRV64] in {
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// mulaw, mulsw are available only in RV64.
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def : Pat<(i32 (add GPR:$rd, (mul GPR:$rs1, GPR:$rs2))),
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(TH_MULAW GPR:$rd, GPR:$rs1, GPR:$rs2)>;
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def : Pat<(i32 (sub GPR:$rd, (mul GPR:$rs1, GPR:$rs2))),
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(TH_MULSW GPR:$rd, GPR:$rs1, GPR:$rs2)>;
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// mulah, mulsh produce a sign-extended result.
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def : Pat<(i32 (add GPR:$rd,
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(mul (sexti16i32 (i32 GPR:$rs1)),
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(sexti16i32 (i32 GPR:$rs2))))),
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(TH_MULAH GPR:$rd, GPR:$rs1, GPR:$rs2)>;
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def : Pat<(i32 (sub GPR:$rd,
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(mul (sexti16i32 (i32 GPR:$rs1)),
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(sexti16i32 (i32 GPR:$rs2))))),
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(TH_MULSH GPR:$rd, GPR:$rs1, GPR:$rs2)>;
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}

‎llvm/test/CodeGen/RISCV/rv64-legal-i32/xtheadmac.ll

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@@ -0,0 +1,123 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -mattr=+xtheadmac -mattr=+m -verify-machineinstrs < %s \
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; RUN: -riscv-experimental-rv64-legal-i32 | FileCheck %s -check-prefix=RV64XTHEADMAC
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define i32 @mula_i32(i32 %a, i32 %b, i32 %c) {
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; RV64XTHEADMAC-LABEL: mula_i32:
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; RV64XTHEADMAC: # %bb.0:
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; RV64XTHEADMAC-NEXT: th.mulaw a0, a1, a2
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; RV64XTHEADMAC-NEXT: ret
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%d = mul i32 %b, %c
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%e = add i32 %a, %d
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ret i32 %e
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}
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define i32 @muls_i32(i32 %a, i32 %b, i32 %c) {
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; RV64XTHEADMAC-LABEL: muls_i32:
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; RV64XTHEADMAC: # %bb.0:
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; RV64XTHEADMAC-NEXT: th.mulsw a0, a1, a2
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; RV64XTHEADMAC-NEXT: ret
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%d = mul i32 %b, %c
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%e = sub i32 %a, %d
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ret i32 %e
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}
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define i64 @mula_i64(i64 %a, i64 %b, i64 %c) {
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; RV64XTHEADMAC-LABEL: mula_i64:
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; RV64XTHEADMAC: # %bb.0:
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; RV64XTHEADMAC-NEXT: th.mula a0, a1, a2
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; RV64XTHEADMAC-NEXT: ret
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%d = mul i64 %b, %c
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%f = add i64 %a, %d
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ret i64 %f
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}
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define i64 @mulaw_i64(i32 %a, i32 %b, i32 %c) {
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; RV64XTHEADMAC-LABEL: mulaw_i64:
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; RV64XTHEADMAC: # %bb.0:
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; RV64XTHEADMAC-NEXT: th.mulaw a0, a1, a2
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; RV64XTHEADMAC-NEXT: ret
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%d = mul i32 %b, %c
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%e = add i32 %a, %d
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%f = sext i32 %e to i64
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ret i64 %f
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}
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define i64 @mulah_i64(i32 %a, i16 %b, i16 %c) {
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; RV64XTHEADMAC-LABEL: mulah_i64:
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; RV64XTHEADMAC: # %bb.0:
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; RV64XTHEADMAC-NEXT: th.mulah a0, a1, a2
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; RV64XTHEADMAC-NEXT: ret
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%d = sext i16 %b to i32
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%e = sext i16 %c to i32
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%f = mul i32 %d, %e
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%g = add i32 %a, %f
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%h = sext i32 %g to i64
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ret i64 %h
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}
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define i64 @muls_i64(i64 %a, i64 %b, i64 %c) {
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; RV64XTHEADMAC-LABEL: muls_i64:
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; RV64XTHEADMAC: # %bb.0:
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; RV64XTHEADMAC-NEXT: th.muls a0, a1, a2
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; RV64XTHEADMAC-NEXT: ret
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%d = mul i64 %b, %c
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%f = sub i64 %a, %d
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ret i64 %f
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}
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define i64 @mulsw_i64(i32 %a, i32 %b, i32 %c) {
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; RV64XTHEADMAC-LABEL: mulsw_i64:
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; RV64XTHEADMAC: # %bb.0:
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; RV64XTHEADMAC-NEXT: th.mulsw a0, a1, a2
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; RV64XTHEADMAC-NEXT: ret
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%d = mul i32 %b, %c
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%e = sub i32 %a, %d
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%f = sext i32 %e to i64
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ret i64 %f
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}
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define i64 @mulsh_i64(i32 %a, i16 %b, i16 %c) {
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; RV64XTHEADMAC-LABEL: mulsh_i64:
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; RV64XTHEADMAC: # %bb.0:
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; RV64XTHEADMAC-NEXT: th.mulsh a0, a1, a2
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; RV64XTHEADMAC-NEXT: ret
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%d = sext i16 %b to i32
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%e = sext i16 %c to i32
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%f = mul i32 %d, %e
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%g = sub i32 %a, %f
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%h = sext i32 %g to i64
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ret i64 %h
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}
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define i32 @commutative1(i32 %A, i32 %B, i32 %C) {
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; RV64XTHEADMAC-LABEL: commutative1:
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; RV64XTHEADMAC: # %bb.0:
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; RV64XTHEADMAC-NEXT: th.mulaw a2, a1, a0
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; RV64XTHEADMAC-NEXT: mv a0, a2
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; RV64XTHEADMAC-NEXT: ret
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%mul = mul nsw i32 %B, %A
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%add = add i32 %mul, %C
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ret i32 %add
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}
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define i32 @commutative2(i32 %A, i32 %B, i32 %C) {
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; RV64XTHEADMAC-LABEL: commutative2:
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; RV64XTHEADMAC: # %bb.0:
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; RV64XTHEADMAC-NEXT: th.mulaw a0, a1, a2
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; RV64XTHEADMAC-NEXT: ret
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%mul = mul nsw i32 %B, %C
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%add = add i32 %mul, %A
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ret i32 %add
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}
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define i32 @commutative3(i32 %A, i32 %B, i32 %C) {
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; RV64XTHEADMAC-LABEL: commutative3:
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; RV64XTHEADMAC: # %bb.0:
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; RV64XTHEADMAC-NEXT: th.mulaw a1, a2, a0
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; RV64XTHEADMAC-NEXT: mv a0, a1
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; RV64XTHEADMAC-NEXT: ret
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%mul = mul nsw i32 %C, %A
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%add = add i32 %mul, %B
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ret i32 %add
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}

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