[RISCV] Remove blank lines at the end of testcases. NFC.

Author: tclin914

llvm/test/CodeGen/RISCV/bittest.ll

@@ -3521,4 +3521,3 @@ define void @bit_64_1_nz_branch_i64(i64 %0) {
 5:
   ret void
 }
-

llvm/test/CodeGen/RISCV/compress-inline-asm.ll

@@ -12,4 +12,3 @@ define i32 @compress_test(i32 %a) {
   %2 = tail call i32 asm "add $0, $1, $2", "=r,r,r"(i32 %a, i32 %1)
   ret i32 %2
 }
-

llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll

@@ -978,4 +978,3 @@ entry:
 declare i64 @llvm.cttz.i64(i64, i1 immarg)
 declare i32 @llvm.cttz.i32(i32, i1 immarg)
 declare i64 @llvm.ctlz.i64(i64, i1 immarg)
-

llvm/test/CodeGen/RISCV/div_minsize.ll

@@ -68,4 +68,3 @@ define i32 @testsize4(i32 %x) minsize nounwind {
   %div = udiv i32 %x, 33
   ret i32 %div
 }
-

llvm/test/CodeGen/RISCV/double-select-icmp.ll

@@ -508,4 +508,3 @@ define double @select_icmp_sgt_zero(i32 signext %a) {
   %2 = select i1 %1, double 0.000000e+00, double 1.000000e+00
   ret double %2
 }
-

llvm/test/CodeGen/RISCV/float-imm.ll

@@ -73,4 +73,3 @@ define float @float_negative_zero(ptr %pf) nounwind {
 ; CHECKZFINX-NEXT:    ret
   ret float -0.0
 }
-

llvm/test/CodeGen/RISCV/float-select-verify.ll

@@ -90,4 +90,3 @@ declare void @foo(i64)
 declare void @bar(float)
 
 declare float @llvm.round.f32(float)
-

llvm/test/CodeGen/RISCV/fmax-fmin.ll

@@ -304,4 +304,3 @@ declare float @llvm.maxnum.f32(float, float)
 declare double @llvm.maxnum.f64(double, double)
 declare float @llvm.minnum.f32(float, float)
 declare double @llvm.minnum.f64(double, double)
-

llvm/test/CodeGen/RISCV/half-select-icmp.ll

@@ -537,4 +537,3 @@ define half @select_icmp_sgt_zero(i32 signext %a) {
   %2 = select i1 %1, half 0.000000e+00, half 1.000000e+00
   ret half %2
 }
-

llvm/test/CodeGen/RISCV/init-array.ll

@@ -27,4 +27,3 @@ define internal void @_GLOBAL__I_a() section ".text.startup" {
 
 ;CTOR: .section .ctors
 ;CTOR-NOT:  section .init_array
-

llvm/test/CodeGen/RISCV/neg-abs.ll

@@ -256,4 +256,3 @@ define i64 @neg_abs64_multiuse(i64 %x, ptr %y) {
   %neg = sub nsw i64 0, %abs
   ret i64 %neg
 }
-

llvm/test/CodeGen/RISCV/pr63816.ll

@@ -80,4 +80,3 @@ define void @test(ptr %0, ptr %1) nounwind {
   store <8 x double> %V2, ptr %1
   ret void
 }
-

llvm/test/CodeGen/RISCV/reduction-formation.ll

@@ -100,4 +100,3 @@ define i32 @reduce_or_4xi32(<4 x i32> %v) {
   %or2 = or i32 %or1, %e3
   ret i32 %or2
 }
-

llvm/test/CodeGen/RISCV/rv32xtheadba.ll

@@ -320,4 +320,3 @@ define i32 @mul288(i32 %a) {
   %c = mul i32 %a, 288
   ret i32 %c
 }
-

llvm/test/CodeGen/RISCV/rv32xtheadbs.ll

@@ -73,4 +73,3 @@ define i64 @th_tst_i64_cmp(i64 %a) nounwind {
   %zext = zext i1 %cmp to i64
   ret i64 %zext
 }
-

llvm/test/CodeGen/RISCV/rv64-legal-i32/xaluo.ll

@@ -1309,4 +1309,3 @@ declare {i32, i1} @llvm.smul.with.overflow.i32(i32, i32) nounwind readnone
 declare {i64, i1} @llvm.smul.with.overflow.i64(i64, i64) nounwind readnone
 declare {i32, i1} @llvm.umul.with.overflow.i32(i32, i32) nounwind readnone
 declare {i64, i1} @llvm.umul.with.overflow.i64(i64, i64) nounwind readnone
-

llvm/test/CodeGen/RISCV/rv64-patchpoint.ll

@@ -21,4 +21,3 @@ entry:
 declare void @llvm.experimental.stackmap(i64, i32, ...)
 declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
 declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
-

llvm/test/CodeGen/RISCV/rv64i-double-softfloat.ll

@@ -55,4 +55,3 @@ entry:
   %conv = tail call i32 @llvm.experimental.constrained.fptosi.i32.f64(double %a, metadata !"fpexcept.strict")
   ret i32 %conv
 }
-

llvm/test/CodeGen/RISCV/rv64xtheadba.ll

@@ -316,4 +316,3 @@ define i64 @mul288(i64 %a) {
   %c = mul i64 %a, 288
   ret i64 %c
 }
-

llvm/test/CodeGen/RISCV/rv64xtheadbs.ll

@@ -69,4 +69,3 @@ define i64 @th_tst_i64_cmp(i64 %a) nounwind {
   %zext = zext i1 %cmp to i64
   ret i64 %zext
 }
-

llvm/test/CodeGen/RISCV/rvv/binop-splats.ll

@@ -619,4 +619,3 @@ define <vscale x 1 x double> @nxv2f64(double %x, double %y) {
   %v = fadd <vscale x 1 x double> %splat.x, %splat.y
   ret <vscale x 1 x double> %v
 }
-

llvm/test/CodeGen/RISCV/rvv/concat-vector-insert-elt.ll

@@ -219,4 +219,3 @@ define void @v4xi64_concat_vector_insert_idx3(ptr %a, ptr %b, i64 %x) {
   store <4 x i64> %ins, ptr %a
   ret void
 }
-

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-binop-splats.ll

@@ -636,4 +636,3 @@ define <1 x double> @v2f64(double %x, double %y) {
   %v = fadd <1 x double> %splat.x, %splat.y
   ret <1 x double> %v
 }
-

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-formation.ll

@@ -982,5 +982,3 @@ define float @reduce_fadd_4xi32_non_associative2(ptr %p) {
   %fadd2 = fadd fast float %fadd1, %e3
   ret float %fadd2
 }
-
-

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store.ll

@@ -1006,4 +1006,3 @@ vector.body:                                      ; preds = %vector.body, %entry
 for.cond.cleanup:                                 ; preds = %vector.body
   ret void
 }
-

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfma-vp.ll

@@ -1037,4 +1037,3 @@ define <32 x double> @vfma_vv_v32f64_unmasked(<32 x double> %va, <32 x double> %
   %v = call <32 x double> @llvm.vp.fma.v32f64(<32 x double> %va, <32 x double> %b, <32 x double> %c, <32 x i1> %m, i32 %evl)
   ret <32 x double> %v
 }
-

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmuladd-vp.ll

@@ -801,4 +801,3 @@ define <32 x double> @vfma_vv_v32f64_unmasked(<32 x double> %va, <32 x double> %
   %v = call <32 x double> @llvm.vp.fmuladd.v32f64(<32 x double> %va, <32 x double> %b, <32 x double> %c, <32 x i1> %m, i32 %evl)
   ret <32 x double> %v
 }
-

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll

@@ -923,4 +923,3 @@ define <2 x i64> @vwmulu_vx_v2i64_i64(ptr %x, ptr %y) {
   %g = mul <2 x i64> %e, %f
   ret <2 x i64> %g
 }
-

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-xsfvcp-x.ll

@@ -1849,4 +1849,3 @@ entry:
 }
 
 declare <16 x float> @llvm.riscv.sf.vc.v.i.se.nxv16f32.iXLen.iXLen(iXLen, iXLen, iXLen, iXLen)
-

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-xsfvcp-xv.ll

@@ -3669,4 +3669,3 @@ entry:
 }
 
 declare <16 x float> @llvm.riscv.sf.vc.v.fv.se.nxv16f32.nxv16f32.iXLen.f32(iXLen, <16 x float>, float, iXLen)
-

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-xsfvcp-xvv.ll

@@ -3669,4 +3669,3 @@ entry:
 }
 
 declare <16 x float> @llvm.riscv.sf.vc.v.fvv.se.nxv16f32.nxv16f32.nxv16i32.f32.iXLen(iXLen, <16 x float>, <16 x i32>, float %rs1, iXLen)
-

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-xsfvcp-xvw.ll

@@ -2694,4 +2694,3 @@ entry:
 }
 
 declare <8 x double> @llvm.riscv.sf.vc.v.fvw.se.nxv8f64.nxv8f32.nxv8i32.f32.iXLen(iXLen, <8 x double>, <8 x i32>, float, iXLen)
-

llvm/test/CodeGen/RISCV/rvv/fptoui-sat.ll

@@ -342,4 +342,3 @@ define <vscale x 4 x i64> @test_signed_v4f16_v4i64(<vscale x 4 x half> %f) {
     %x = call <vscale x 4 x i64> @llvm.fptoui.sat.nxv4f16.nxv4i64(<vscale x 4 x half> %f)
     ret <vscale x 4 x i64> %x
 }
-

llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv32.ll

@@ -726,4 +726,3 @@ define <vscale x 8 x i1> @trunc_nxv8i64_nxv8i1(<vscale x 8 x i64> %v) {
   %r = trunc <vscale x 8 x i64> %v to <vscale x 8 x i1>
   ret <vscale x 8 x i1> %r
 }
-

llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv64.ll

@@ -726,4 +726,3 @@ define <vscale x 8 x i1> @trunc_nxv8i64_nxv8i1(<vscale x 8 x i64> %v) {
   %r = trunc <vscale x 8 x i64> %v to <vscale x 8 x i1>
   ret <vscale x 8 x i1> %r
 }
-

llvm/test/CodeGen/RISCV/rvv/vaesdf.ll

@@ -123,4 +123,3 @@ entry:
 
   ret <vscale x 16 x i32> %a
 }
-

llvm/test/CodeGen/RISCV/rvv/vaesdm.ll

@@ -123,4 +123,3 @@ entry:
 
   ret <vscale x 16 x i32> %a
 }
-

llvm/test/CodeGen/RISCV/rvv/vaesef.ll

@@ -123,4 +123,3 @@ entry:
 
   ret <vscale x 16 x i32> %a
 }
-

llvm/test/CodeGen/RISCV/rvv/vaesem.ll

@@ -123,4 +123,3 @@ entry:
 
   ret <vscale x 16 x i32> %a
 }
-

llvm/test/CodeGen/RISCV/rvv/vaesz.ll

@@ -63,4 +63,3 @@ entry:
 
   ret <vscale x 16 x i32> %a
 }
-

llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll

@@ -2003,4 +2003,3 @@ define <vscale x 8 x i64> @vandn_vx_swapped_nxv8i64(i64 %x, <vscale x 8 x i64> %
   %b = and <vscale x 8 x i64> %splat, %y
   ret <vscale x 8 x i64> %b
 }
-

llvm/test/CodeGen/RISCV/rvv/vandn-vp.ll

@@ -1429,4 +1429,3 @@ define <vscale x 8 x i64> @vandn_vx_vp_nxv8i64(i64 %a, <vscale x 8 x i64> %b, <v
   %x = call <vscale x 8 x i64> @llvm.vp.and.nxv8i64(<vscale x 8 x i64> %b, <vscale x 8 x i64> %splat.not.a, <vscale x 8 x i1> %mask, i32 %evl)
   ret <vscale x 8 x i64> %x
 }
-

llvm/test/CodeGen/RISCV/rvv/vector-splice.ll

@@ -2370,4 +2370,3 @@ define <vscale x 8 x double> @splice_nxv8f64_offset_max(<vscale x 8 x double> %a
 }
 
 attributes #0 = { vscale_range(2,0) }
-

llvm/test/CodeGen/RISCV/rvv/vexts-sdnode.ll

@@ -617,4 +617,3 @@ define <vscale x 8 x i64> @vzext_nxv8i32_nxv8i64(<vscale x 8 x i32> %va) {
   %evec = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
   ret <vscale x 8 x i64> %evec
 }
-

llvm/test/CodeGen/RISCV/rvv/vmarith-sdnode.ll

@@ -476,4 +476,3 @@ define <vscale x 16 x i1> @vmorn_vv_nxv16i1(<vscale x 16 x i1> %va, <vscale x 16
   %vc = or <vscale x 16 x i1> %va, %not
   ret <vscale x 16 x i1> %vc
 }
-

llvm/test/CodeGen/RISCV/rvv/vmax-sdnode.ll

@@ -889,4 +889,3 @@ define <vscale x 8 x i64> @vmax_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
   %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i64> %va, <vscale x 8 x i64> %splat
   ret <vscale x 8 x i64> %vc
 }
-

llvm/test/CodeGen/RISCV/rvv/vmin-sdnode.ll

@@ -889,4 +889,3 @@ define <vscale x 8 x i64> @vmin_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
   %vc = select <vscale x 8 x i1> %cmp, <vscale x 8 x i64> %va, <vscale x 8 x i64> %splat
   ret <vscale x 8 x i64> %vc
 }
-

llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll

@@ -1004,4 +1004,3 @@ define <vscale x 8 x i32> @vmul_vi_mask_nxv8i32(<vscale x 8 x i32> %va, <vscale
   %vc = mul <vscale x 8 x i32> %va, %vs
   ret <vscale x 8 x i32> %vc
 }
-

llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll

@@ -1299,4 +1299,3 @@ define <vscale x 8 x i64> @vrem_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
   %vc = srem <vscale x 8 x i64> %va, %splat
   ret <vscale x 8 x i64> %vc
 }
-

llvm/test/CodeGen/RISCV/rvv/vrol-sdnode.ll

@@ -1154,4 +1154,3 @@ define <vscale x 8 x i64> @vrol_vx_nxv8i64(<vscale x 8 x i64> %a, i64 %b) {
   %x = call <vscale x 8 x i64> @llvm.fshl.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %a, <vscale x 8 x i64> %b.splat)
   ret <vscale x 8 x i64> %x
 }
-

llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll

@@ -1976,4 +1976,3 @@ define <vscale x 8 x i64> @vror_vi_rotl_nxv8i64(<vscale x 8 x i64> %a) {
   %x = call <vscale x 8 x i64> @llvm.fshl.nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %a, <vscale x 8 x i64> shufflevector(<vscale x 8 x i64> insertelement(<vscale x 8 x i64> poison, i64 1, i32 0), <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer))
   ret <vscale x 8 x i64> %x
 }
-

llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode.ll

@@ -581,4 +581,3 @@ define <vscale x 8 x i64> @vrsub_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
   %vc = sub <vscale x 8 x i64> %splat, %va
   ret <vscale x 8 x i64> %vc
 }
-

llvm/test/CodeGen/RISCV/rvv/vsm4r.ll

@@ -123,4 +123,3 @@ entry:
 
   ret <vscale x 16 x i32> %a
 }
-

llvm/test/CodeGen/RISCV/rvv/vsplats-i1.ll

@@ -209,4 +209,3 @@ define <vscale x 4 x i1> @splat_idx_nxv4i32(<vscale x 4 x i1> %v, i64 %idx) {
   %splat = shufflevector <vscale x 4 x i1> %ins, <vscale x 4 x i1> poison, <vscale x 4 x i32> zeroinitializer
   ret <vscale x 4 x i1> %splat
 }
-

llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode.ll

@@ -313,4 +313,3 @@ define <vscale x 8 x i32> @vtrunc_nxv8i64_nxv8i32(<vscale x 8 x i64> %va) {
   %tvec = trunc <vscale x 8 x i64> %va to <vscale x 8 x i32>
   ret <vscale x 8 x i32> %tvec
 }
-

llvm/test/CodeGen/RISCV/rvv/xsfvcp-x.ll

@@ -2239,4 +2239,3 @@ entry:
 }
 
 declare <vscale x 16 x float> @llvm.riscv.sf.vc.v.i.se.nxv16f32.iXLen.iXLen(iXLen, iXLen, iXLen, iXLen)
-

llvm/test/CodeGen/RISCV/rvv/xsfvcp-xv.ll

@@ -3669,4 +3669,3 @@ entry:
 }
 
 declare <vscale x 16 x float> @llvm.riscv.sf.vc.v.fv.se.nxv16f32.nxv16f32.iXLen.f32(iXLen, <vscale x 16 x float>, float, iXLen)
-

llvm/test/CodeGen/RISCV/rvv/xsfvcp-xvv.ll

@@ -3687,4 +3687,3 @@ entry:
 }
 
 declare <vscale x 16 x float> @llvm.riscv.sf.vc.v.fvv.se.nxv16f32.nxv16f32.nxv16i32.f32.iXLen(iXLen, <vscale x 16 x float>, <vscale x 16 x i32>, float %rs1, iXLen)
-

llvm/test/CodeGen/RISCV/rvv/xsfvcp-xvw.ll

@@ -2694,4 +2694,3 @@ entry:
 }
 
 declare <vscale x 8 x double> @llvm.riscv.sf.vc.v.fvw.se.nxv8f64.nxv8f32.nxv8i32.f32.iXLen(iXLen, <vscale x 8 x double>, <vscale x 8 x i32>, float, iXLen)
-

llvm/test/CodeGen/RISCV/saverestore-scs.ll

@@ -37,4 +37,3 @@ define void @callee_scs() nounwind shadowcallstack {
   store volatile [30 x i32] %val, ptr @var2
   ret void
 }
-

llvm/test/CodeGen/RISCV/split-urem-by-constant.ll

@@ -393,4 +393,3 @@ define iXLen2 @test_urem_12(iXLen2 %x) nounwind {
   %a = urem iXLen2 %x, 12
   ret iXLen2 %a
 }
-

llvm/test/CodeGen/RISCV/switch-width.ll

@@ -314,4 +314,3 @@ return:
   %retval = phi i32 [ -1, %sw.default ], [ 0, %sw.bb0 ], [ 1, %sw.bb1 ]
   ret i32 %retval
 }
-

llvm/test/CodeGen/RISCV/unroll-loop-cse.ll

@@ -89,4 +89,3 @@ define signext i32 @unroll_loop_cse() {
   %26 = phi i32 [ 1, %0 ], [ 1, %4 ], [ 1, %8 ], [ 1, %12 ], [ 1, %16 ], [ %24, %20 ]
   ret i32 %26
 }
-

llvm/test/CodeGen/RISCV/xaluo.ll

@@ -5927,4 +5927,3 @@ declare {i32, i1} @llvm.smul.with.overflow.i32(i32, i32) nounwind readnone
 declare {i64, i1} @llvm.smul.with.overflow.i64(i64, i64) nounwind readnone
 declare {i32, i1} @llvm.umul.with.overflow.i32(i32, i32) nounwind readnone
 declare {i64, i1} @llvm.umul.with.overflow.i64(i64, i64) nounwind readnone
-

llvm/test/CodeGen/RISCV/zbb-cmp-combine.ll

@@ -315,4 +315,3 @@ define i1 @no_same_ops(i64 %c, i64 %a, i64 %b) {
   %res = or i1 %l0, %l1
   ret i1 %res
 }
-

llvm/test/Transforms/InterleavedAccess/RISCV/interleaved-accesses.ll

@@ -364,15 +364,3 @@ define void @load_factor2_fp128(ptr %ptr) {
   %v1 = shufflevector <4 x fp128> %interleaved.vec, <4 x fp128> poison, <2 x i32> <i32 1, i32 3>
   ret void
 }
-
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