Revert "Move assertion for AdjustsStack from PEI to MachineVerifier. (#85698)"

This reverts commit 05bde30.

Reverting due to verifier complaints with expensive checks on build-bot.

Author: JonPsson1

llvm/lib/CodeGen/MachineVerifier.cpp

@@ -3697,9 +3697,6 @@ void MachineVerifier::verifyStackFrame() {
       if (I.getOpcode() == FrameSetupOpcode) {
         if (BBState.ExitIsSetup)
           report("FrameSetup is after another FrameSetup", &I);
-        if (!MRI->isSSA() && !MF->getFrameInfo().adjustsStack())
-          report("AdjustsStack not set in presence of a frame pseudo "
-                 "instruction.", &I);
         BBState.ExitValue -= TII->getFrameTotalSize(I);
         BBState.ExitIsSetup = true;
       }
@@ -3715,9 +3712,6 @@ void MachineVerifier::verifyStackFrame() {
           errs() << "FrameDestroy <" << Size << "> is after FrameSetup <"
               << AbsSPAdj << ">.\n";
         }
-        if (!MRI->isSSA() && !MF->getFrameInfo().adjustsStack())
-          report("AdjustsStack not set in presence of a frame pseudo "
-                 "instruction.", &I);
         BBState.ExitValue += Size;
         BBState.ExitIsSetup = false;
       }

llvm/lib/CodeGen/PrologEpilogInserter.cpp

@@ -372,6 +372,8 @@ void PEI::calculateCallFrameInfo(MachineFunction &MF) {
   MFI.computeMaxCallFrameSize(MF, &FrameSDOps);
   assert(MFI.getMaxCallFrameSize() <= MaxCFSIn &&
          "Recomputing MaxCFS gave a larger value.");
+  assert((FrameSDOps.empty() || MF.getFrameInfo().adjustsStack()) &&
+         "AdjustsStack not set in presence of a frame pseudo instruction.");
 
   if (TFI->canSimplifyCallFramePseudos(MF)) {
     // If call frames are not being included as part of the stack frame, and

llvm/test/CodeGen/AArch64/clear-dead-implicit-def-impdef.mir

@@ -2,8 +2,6 @@
 # RUN: llc -mtriple=arm64-apple-macosx -mcpu=apple-m1 -verify-regalloc -run-pass=greedy -o - %s | FileCheck %s
 ---
 name:            func
-frameInfo:
-  adjustsStack:    true
 tracksRegLiveness: true
 body:             |
   bb.0:

llvm/test/CodeGen/AArch64/implicit-def-remat-requires-impdef-check.mir

@@ -22,7 +22,6 @@
 name:            inst_stores_to_dead_spill_implicit_def_impdef
 tracksRegLiveness: true
 frameInfo:
-  adjustsStack:    true
   hasCalls:        true
 body:             |
   bb.0:
@@ -60,7 +59,6 @@ body:             |
 name:            inst_stores_to_dead_spill_movimm_impdef
 tracksRegLiveness: true
 frameInfo:
-  adjustsStack:    true
   hasCalls:        true
 body:             |
   bb.0:

llvm/test/CodeGen/AArch64/implicit-def-with-impdef-greedy-assert.mir

@@ -3,8 +3,6 @@
 
 ---
 name:            widget
-frameInfo:
-  adjustsStack:    true
 tracksRegLiveness: true
 jumpTable:
   kind:            label-difference32

llvm/test/CodeGen/AMDGPU/fold-restore-undef-use.mir

@@ -7,8 +7,6 @@
 
 ---
 name:            restore_undef_copy_use
-frameInfo:
-  adjustsStack:    true
 tracksRegLiveness: true
 machineFunctionInfo:
   maxKernArgAlign: 1

llvm/test/CodeGen/AMDGPU/greedy-alloc-fail-sgpr1024-spill.mir

@@ -13,7 +13,6 @@
 name:            greedy_fail_alloc_sgpr1024_spill
 tracksRegLiveness: true
 frameInfo:
-  adjustsStack:    true
   hasCalls:        true
 machineFunctionInfo:
   explicitKernArgSize: 16

llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir

@@ -24,7 +24,6 @@ registers:
   - { id: 10, class: sreg_64_xexec, preferred-register: '$vcc' }
 frameInfo:
   maxAlignment:    1
-  adjustsStack:    true
   hasCalls:        true
 machineFunctionInfo:
   maxKernArgAlign: 1

llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir

@@ -180,8 +180,6 @@ exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
-frameInfo:
-  adjustsStack:    true
 tracksRegLiveness: true
 liveins:
   - { reg: '$vgpr0', virtual-reg: '%0' }

llvm/test/CodeGen/AMDGPU/sgpr-spill-wrong-stack-id.mir

@@ -78,7 +78,6 @@
 name:            sgpr_spill_wrong_stack_id
 tracksRegLiveness: true
 frameInfo:
-  adjustsStack:    true
   hasCalls:        true
 machineFunctionInfo:
   scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3

llvm/test/CodeGen/AMDGPU/snippet-copy-bundle-regression.mir

@@ -21,7 +21,6 @@
 name:            kernel
 tracksRegLiveness: true
 frameInfo:
-  adjustsStack:    true
   hasCalls:        true
 machineFunctionInfo:
   isEntryFunction: true

llvm/test/CodeGen/AMDGPU/virtregrewrite-undef-identity-copy.mir

@@ -20,7 +20,6 @@ name:            undef_identity_copy
 tracksRegLiveness: true
 frameInfo:
   maxAlignment:    4
-  adjustsStack:    true
   hasCalls:        true
 machineFunctionInfo:
   isEntryFunction: true

llvm/test/CodeGen/ARM/no-register-coalescing-in-returnsTwice.mir

@@ -86,8 +86,6 @@
 ---
 name:            main
 exposesReturnsTwice: true
-frameInfo:
-  adjustsStack:    true
 stack:
   - { id: 0, name: P0, size: 80, alignment: 8, local-offset: -80 }
   - { id: 1, name: jb1, size: 160, alignment: 8, local-offset: -240 }

llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir

@@ -135,7 +135,7 @@ frameInfo:
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    0
-  adjustsStack:    true
+  adjustsStack:    false
   hasCalls:        true
   maxCallFrameSize: 0
   hasOpaqueSPAdjustment: false

llvm/test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir

@@ -24,8 +24,6 @@
 ---
 name:            autogen_SD21418
 alignment:       4
-frameInfo:
-  adjustsStack:    true
 tracksRegLiveness: true
 registers:       
   - { id: 0, class: vr128bit }

llvm/test/CodeGen/SystemZ/clear-liverange-spillreg.mir

@@ -157,7 +157,6 @@ registers:
   - { id: 129, class: grx32bit }
   - { id: 130, class: fp64bit }
 frameInfo:
-  adjustsStack:    true
   hasCalls:        true
 body:             |
   bb.0:

llvm/test/CodeGen/SystemZ/int-cmp-56.mir

@@ -48,7 +48,6 @@ liveins:
   - { reg: '$r2d', virtual-reg: '%0' }
 frameInfo:
   maxAlignment:    1
-  adjustsStack:    true
   hasCalls:        true
 machineFunctionInfo: {}
 body:             |
@@ -126,7 +125,6 @@ liveins:
   - { reg: '$r2d', virtual-reg: '%0' }
 frameInfo:
   maxAlignment:    1
-  adjustsStack:    true
   hasCalls:        true
 machineFunctionInfo: {}
 body:             |
@@ -204,7 +202,6 @@ liveins:
   - { reg: '$r2d', virtual-reg: '%0' }
 frameInfo:
   maxAlignment:    1
-  adjustsStack:    true
   hasCalls:        true
 machineFunctionInfo: {}
 body:             |
@@ -282,7 +279,6 @@ liveins:
   - { reg: '$r2d', virtual-reg: '%0' }
 frameInfo:
   maxAlignment:    1
-  adjustsStack:    true
   hasCalls:        true
 machineFunctionInfo: {}
 body:             |

llvm/test/CodeGen/SystemZ/regcoal-subranges-update.mir

@@ -48,8 +48,6 @@ body:             |
 # represented for the value carried by %7.
 ---
 name:            segfault
-frameInfo:
-  adjustsStack:    true
 tracksRegLiveness: true
 liveins:         []
 body:             |

llvm/test/CodeGen/X86/callbr-asm-kill.mir

@@ -45,7 +45,6 @@ liveins:
   - { reg: '$rsi', virtual-reg: '%3' }
 frameInfo:
   maxAlignment:    1
-  adjustsStack:    true
   hasCalls:        true
 machineFunctionInfo: {}
 body:             |

llvm/test/CodeGen/X86/regalloc-copy-hints.mir

@@ -103,7 +103,6 @@ registers:
   - { id: 82, class: gr32 }
 frameInfo:       
   maxAlignment:    4
-  adjustsStack:    true
   hasCalls:        true
 fixedStack:      
   - { id: 0, size: 4, alignment: 4, stack-id: default, isImmutable: true }

llvm/test/CodeGen/X86/statepoint-fastregalloc.mir

@@ -5,8 +5,6 @@
 # Tied def/use must be assigned to the same register.
 ---
 name:            test_relocate
-frameInfo:
-  adjustsStack:    true
 tracksRegLiveness: true
 body:             |
   bb.0.entry:
@@ -26,8 +24,6 @@ body:             |
 # These regmasks have no real meaning and chosen to allow only single register to be assignable ($rbp)
 ---
 name:            test_relocate_multi_regmasks
-frameInfo:
-  adjustsStack:    true
 tracksRegLiveness: true
 body:             |
   bb.0.entry:

llvm/test/CodeGen/X86/statepoint-invoke-ra-enter-at-end.mir

@@ -231,7 +231,7 @@ frameInfo:
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
-  adjustsStack:    true
+  adjustsStack:    false
   hasCalls:        true
   stackProtector:  ''
   maxCallFrameSize: 4294967295

llvm/test/CodeGen/X86/statepoint-invoke-ra-hoist-copies.mir

@@ -398,7 +398,7 @@ frameInfo:
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
-  adjustsStack:    true
+  adjustsStack:    false
   hasCalls:        true
   stackProtector:  ''
   maxCallFrameSize: 4294967295

llvm/test/CodeGen/X86/statepoint-invoke-ra-inline-spiller.mir

@@ -175,7 +175,7 @@ frameInfo:
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    4
-  adjustsStack:    true
+  adjustsStack:    false
   hasCalls:        true
   stackProtector:  ''
   maxCallFrameSize: 4294967295

llvm/test/CodeGen/X86/statepoint-invoke-ra-remove-back-copies.mir

@@ -226,7 +226,7 @@ frameInfo:
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    4
-  adjustsStack:    true
+  adjustsStack:    false
   hasCalls:        true
   stackProtector:  ''
   maxCallFrameSize: 4294967295

llvm/test/CodeGen/X86/statepoint-invoke-ra.mir

@@ -172,7 +172,7 @@ frameInfo:
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    4
-  adjustsStack:    true
+  adjustsStack:    false
   hasCalls:        true
   stackProtector:  ''
   maxCallFrameSize: 4294967295

llvm/test/CodeGen/X86/statepoint-vreg-folding.mir

@@ -114,7 +114,7 @@ frameInfo:
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    8
-  adjustsStack:    true
+  adjustsStack:    false
   hasCalls:        true
   stackProtector:  ''
   maxCallFrameSize: 4294967295

llvm/test/DebugInfo/MIR/InstrRef/phi-coalescing.mir

@@ -106,7 +106,6 @@ liveins:
   - { reg: '$rsi', virtual-reg: '%5' }
 frameInfo:
   maxAlignment:    1
-  adjustsStack:    true
   hasCalls:        true
 machineFunctionInfo: {}
 body:             |

llvm/test/DebugInfo/MIR/Mips/livedebugvars-stop-trimming-loc.mir

@@ -71,8 +71,6 @@
 ---
 name:            fn2
 alignment:       4
-frameInfo:
-  adjustsStack:    true
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gpr32, preferred-register: '' }