[RISC-V][ISel] Remove redundant czero.eqz like 'czero.eqz a0, a0, a0'

Signed-off-by: Zhijin Zeng <[email protected]>

Author: zengdage

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -16164,23 +16164,31 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
   case ISD::SELECT:
     return performSELECTCombine(N, DAG, Subtarget);
   case RISCVISD::CZERO_EQZ:
-  case RISCVISD::CZERO_NEZ:
+  case RISCVISD::CZERO_NEZ: {
+    SDValue LHS = N->getOperand(0);
+    SDValue RHS = N->getOperand(1);
     // czero_eq X, (xor Y, 1) -> czero_ne X, Y if Y is 0 or 1.
     // czero_ne X, (xor Y, 1) -> czero_eq X, Y if Y is 0 or 1.
-    if (N->getOperand(1).getOpcode() == ISD::XOR &&
-        isOneConstant(N->getOperand(1).getOperand(1))) {
-      SDValue Cond = N->getOperand(1).getOperand(0);
+    if (RHS.getOpcode() == ISD::XOR && isOneConstant(RHS.getOperand(1))) {
+      SDValue Cond = RHS.getOperand(0);
       APInt Mask = APInt::getBitsSetFrom(Cond.getValueSizeInBits(), 1);
       if (DAG.MaskedValueIsZero(Cond, Mask)) {
         unsigned NewOpc = N->getOpcode() == RISCVISD::CZERO_EQZ
                               ? RISCVISD::CZERO_NEZ
                               : RISCVISD::CZERO_EQZ;
-        return DAG.getNode(NewOpc, SDLoc(N), N->getValueType(0),
-                           N->getOperand(0), Cond);
+        return DAG.getNode(NewOpc, SDLoc(N), N->getValueType(0), LHS, Cond);
       }
     }
+    // czero_eqz x, (setcc x, 0, ne) -> x
+    // czero_nez x, (setcc x, 0, eq) -> x
+    if (RHS.getOpcode() == ISD::SETCC && isNullConstant(RHS.getOperand(1)) &&
+        cast<CondCodeSDNode>(RHS.getOperand(2))->get() ==
+            (N->getOpcode() == RISCVISD::CZERO_EQZ ? ISD::CondCode::SETNE
+                                                   : ISD::CondCode::SETEQ) &&
+        LHS == RHS.getOperand(0))
+      return LHS;
     return SDValue();
-
+  }
   case RISCVISD::SELECT_CC: {
     // Transform
     SDValue LHS = N->getOperand(0);

llvm/test/CodeGen/RISCV/select.ll

@@ -1887,7 +1887,6 @@ define void @select_redundant_czero_eqz1(ptr %0, ptr %1) {
 ; RV64IMXVTCONDOPS-NEXT:    lui a2, %hi(select_redundant_czero_eqz_data)
 ; RV64IMXVTCONDOPS-NEXT:    addi a2, a2, %lo(select_redundant_czero_eqz_data)
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskcn a2, a2, a0
-; RV64IMXVTCONDOPS-NEXT:    vt.maskc a0, a0, a0
 ; RV64IMXVTCONDOPS-NEXT:    or a0, a2, a0
 ; RV64IMXVTCONDOPS-NEXT:    sd a0, 0(a1)
 ; RV64IMXVTCONDOPS-NEXT:    ret
@@ -1897,7 +1896,6 @@ define void @select_redundant_czero_eqz1(ptr %0, ptr %1) {
 ; RV32IMZICOND-NEXT:    lui a2, %hi(select_redundant_czero_eqz_data)
 ; RV32IMZICOND-NEXT:    addi a2, a2, %lo(select_redundant_czero_eqz_data)
 ; RV32IMZICOND-NEXT:    czero.nez a2, a2, a0
-; RV32IMZICOND-NEXT:    czero.eqz a0, a0, a0
 ; RV32IMZICOND-NEXT:    or a0, a2, a0
 ; RV32IMZICOND-NEXT:    sw a0, 0(a1)
 ; RV32IMZICOND-NEXT:    ret
@@ -1907,7 +1905,6 @@ define void @select_redundant_czero_eqz1(ptr %0, ptr %1) {
 ; RV64IMZICOND-NEXT:    lui a2, %hi(select_redundant_czero_eqz_data)
 ; RV64IMZICOND-NEXT:    addi a2, a2, %lo(select_redundant_czero_eqz_data)
 ; RV64IMZICOND-NEXT:    czero.nez a2, a2, a0
-; RV64IMZICOND-NEXT:    czero.eqz a0, a0, a0
 ; RV64IMZICOND-NEXT:    or a0, a2, a0
 ; RV64IMZICOND-NEXT:    sd a0, 0(a1)
 ; RV64IMZICOND-NEXT:    ret
@@ -1944,7 +1941,6 @@ define void @select_redundant_czero_eqz2(ptr %0, ptr %1) {
 ; RV64IMXVTCONDOPS-NEXT:    lui a2, %hi(select_redundant_czero_eqz_data)
 ; RV64IMXVTCONDOPS-NEXT:    addi a2, a2, %lo(select_redundant_czero_eqz_data)
 ; RV64IMXVTCONDOPS-NEXT:    vt.maskcn a2, a2, a0
-; RV64IMXVTCONDOPS-NEXT:    vt.maskc a0, a0, a0
 ; RV64IMXVTCONDOPS-NEXT:    or a0, a0, a2
 ; RV64IMXVTCONDOPS-NEXT:    sd a0, 0(a1)
 ; RV64IMXVTCONDOPS-NEXT:    ret
@@ -1954,7 +1950,6 @@ define void @select_redundant_czero_eqz2(ptr %0, ptr %1) {
 ; RV32IMZICOND-NEXT:    lui a2, %hi(select_redundant_czero_eqz_data)
 ; RV32IMZICOND-NEXT:    addi a2, a2, %lo(select_redundant_czero_eqz_data)
 ; RV32IMZICOND-NEXT:    czero.nez a2, a2, a0
-; RV32IMZICOND-NEXT:    czero.eqz a0, a0, a0
 ; RV32IMZICOND-NEXT:    or a0, a0, a2
 ; RV32IMZICOND-NEXT:    sw a0, 0(a1)
 ; RV32IMZICOND-NEXT:    ret
@@ -1964,7 +1959,6 @@ define void @select_redundant_czero_eqz2(ptr %0, ptr %1) {
 ; RV64IMZICOND-NEXT:    lui a2, %hi(select_redundant_czero_eqz_data)
 ; RV64IMZICOND-NEXT:    addi a2, a2, %lo(select_redundant_czero_eqz_data)
 ; RV64IMZICOND-NEXT:    czero.nez a2, a2, a0
-; RV64IMZICOND-NEXT:    czero.eqz a0, a0, a0
 ; RV64IMZICOND-NEXT:    or a0, a0, a2
 ; RV64IMZICOND-NEXT:    sd a0, 0(a1)
 ; RV64IMZICOND-NEXT:    ret