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[RISC-V][ISel] Remove redundant czero.eqz like 'czero.eqz a0, a0, a0'
Signed-off-by: Zhijin Zeng <[email protected]>
1 parent 6cac8a7 commit 9ecc11c

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2 files changed

+15
-13
lines changed

2 files changed

+15
-13
lines changed

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 15 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -16164,23 +16164,31 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
1616416164
case ISD::SELECT:
1616516165
return performSELECTCombine(N, DAG, Subtarget);
1616616166
case RISCVISD::CZERO_EQZ:
16167-
case RISCVISD::CZERO_NEZ:
16167+
case RISCVISD::CZERO_NEZ: {
16168+
SDValue LHS = N->getOperand(0);
16169+
SDValue RHS = N->getOperand(1);
1616816170
// czero_eq X, (xor Y, 1) -> czero_ne X, Y if Y is 0 or 1.
1616916171
// czero_ne X, (xor Y, 1) -> czero_eq X, Y if Y is 0 or 1.
16170-
if (N->getOperand(1).getOpcode() == ISD::XOR &&
16171-
isOneConstant(N->getOperand(1).getOperand(1))) {
16172-
SDValue Cond = N->getOperand(1).getOperand(0);
16172+
if (RHS.getOpcode() == ISD::XOR && isOneConstant(RHS.getOperand(1))) {
16173+
SDValue Cond = RHS.getOperand(0);
1617316174
APInt Mask = APInt::getBitsSetFrom(Cond.getValueSizeInBits(), 1);
1617416175
if (DAG.MaskedValueIsZero(Cond, Mask)) {
1617516176
unsigned NewOpc = N->getOpcode() == RISCVISD::CZERO_EQZ
1617616177
? RISCVISD::CZERO_NEZ
1617716178
: RISCVISD::CZERO_EQZ;
16178-
return DAG.getNode(NewOpc, SDLoc(N), N->getValueType(0),
16179-
N->getOperand(0), Cond);
16179+
return DAG.getNode(NewOpc, SDLoc(N), N->getValueType(0), LHS, Cond);
1618016180
}
1618116181
}
16182+
// czero_eqz x, (setcc x, 0, ne) -> x
16183+
// czero_nez x, (setcc x, 0, eq) -> x
16184+
if (RHS.getOpcode() == ISD::SETCC && isNullConstant(RHS.getOperand(1)) &&
16185+
cast<CondCodeSDNode>(RHS.getOperand(2))->get() ==
16186+
(N->getOpcode() == RISCVISD::CZERO_EQZ ? ISD::CondCode::SETNE
16187+
: ISD::CondCode::SETEQ) &&
16188+
LHS == RHS.getOperand(0))
16189+
return LHS;
1618216190
return SDValue();
16183-
16191+
}
1618416192
case RISCVISD::SELECT_CC: {
1618516193
// Transform
1618616194
SDValue LHS = N->getOperand(0);

llvm/test/CodeGen/RISCV/select.ll

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1887,7 +1887,6 @@ define void @select_redundant_czero_eqz1(ptr %0, ptr %1) {
18871887
; RV64IMXVTCONDOPS-NEXT: lui a2, %hi(select_redundant_czero_eqz_data)
18881888
; RV64IMXVTCONDOPS-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data)
18891889
; RV64IMXVTCONDOPS-NEXT: vt.maskcn a2, a2, a0
1890-
; RV64IMXVTCONDOPS-NEXT: vt.maskc a0, a0, a0
18911890
; RV64IMXVTCONDOPS-NEXT: or a0, a2, a0
18921891
; RV64IMXVTCONDOPS-NEXT: sd a0, 0(a1)
18931892
; RV64IMXVTCONDOPS-NEXT: ret
@@ -1897,7 +1896,6 @@ define void @select_redundant_czero_eqz1(ptr %0, ptr %1) {
18971896
; RV32IMZICOND-NEXT: lui a2, %hi(select_redundant_czero_eqz_data)
18981897
; RV32IMZICOND-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data)
18991898
; RV32IMZICOND-NEXT: czero.nez a2, a2, a0
1900-
; RV32IMZICOND-NEXT: czero.eqz a0, a0, a0
19011899
; RV32IMZICOND-NEXT: or a0, a2, a0
19021900
; RV32IMZICOND-NEXT: sw a0, 0(a1)
19031901
; RV32IMZICOND-NEXT: ret
@@ -1907,7 +1905,6 @@ define void @select_redundant_czero_eqz1(ptr %0, ptr %1) {
19071905
; RV64IMZICOND-NEXT: lui a2, %hi(select_redundant_czero_eqz_data)
19081906
; RV64IMZICOND-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data)
19091907
; RV64IMZICOND-NEXT: czero.nez a2, a2, a0
1910-
; RV64IMZICOND-NEXT: czero.eqz a0, a0, a0
19111908
; RV64IMZICOND-NEXT: or a0, a2, a0
19121909
; RV64IMZICOND-NEXT: sd a0, 0(a1)
19131910
; RV64IMZICOND-NEXT: ret
@@ -1944,7 +1941,6 @@ define void @select_redundant_czero_eqz2(ptr %0, ptr %1) {
19441941
; RV64IMXVTCONDOPS-NEXT: lui a2, %hi(select_redundant_czero_eqz_data)
19451942
; RV64IMXVTCONDOPS-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data)
19461943
; RV64IMXVTCONDOPS-NEXT: vt.maskcn a2, a2, a0
1947-
; RV64IMXVTCONDOPS-NEXT: vt.maskc a0, a0, a0
19481944
; RV64IMXVTCONDOPS-NEXT: or a0, a0, a2
19491945
; RV64IMXVTCONDOPS-NEXT: sd a0, 0(a1)
19501946
; RV64IMXVTCONDOPS-NEXT: ret
@@ -1954,7 +1950,6 @@ define void @select_redundant_czero_eqz2(ptr %0, ptr %1) {
19541950
; RV32IMZICOND-NEXT: lui a2, %hi(select_redundant_czero_eqz_data)
19551951
; RV32IMZICOND-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data)
19561952
; RV32IMZICOND-NEXT: czero.nez a2, a2, a0
1957-
; RV32IMZICOND-NEXT: czero.eqz a0, a0, a0
19581953
; RV32IMZICOND-NEXT: or a0, a0, a2
19591954
; RV32IMZICOND-NEXT: sw a0, 0(a1)
19601955
; RV32IMZICOND-NEXT: ret
@@ -1964,7 +1959,6 @@ define void @select_redundant_czero_eqz2(ptr %0, ptr %1) {
19641959
; RV64IMZICOND-NEXT: lui a2, %hi(select_redundant_czero_eqz_data)
19651960
; RV64IMZICOND-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data)
19661961
; RV64IMZICOND-NEXT: czero.nez a2, a2, a0
1967-
; RV64IMZICOND-NEXT: czero.eqz a0, a0, a0
19681962
; RV64IMZICOND-NEXT: or a0, a0, a2
19691963
; RV64IMZICOND-NEXT: sd a0, 0(a1)
19701964
; RV64IMZICOND-NEXT: ret

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