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AMDGPU: Add more tests for vector typed atomicrmw fadd
Some cases should be legal for gfx940.
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‎llvm/test/CodeGen/AMDGPU/GlobalISel/fp-atomics-gfx940.ll

Lines changed: 161 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -209,4 +209,165 @@ define <2 x i16> @local_atomic_fadd_v2bf16_rtn(ptr addrspace(3) %ptr, <2 x i16>
209209
ret <2 x i16> %ret
210210
}
211211

212+
define <2 x half> @local_atomic_fadd_ret_v2f16_offset(ptr addrspace(3) %ptr, <2 x half> %val) {
213+
; GFX940-LABEL: local_atomic_fadd_ret_v2f16_offset:
214+
; GFX940: ; %bb.0:
215+
; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
216+
; GFX940-NEXT: ds_read_b32 v2, v0 offset:65532
217+
; GFX940-NEXT: s_mov_b64 s[0:1], 0
218+
; GFX940-NEXT: .LBB15_1: ; %atomicrmw.start
219+
; GFX940-NEXT: ; =>This Inner Loop Header: Depth=1
220+
; GFX940-NEXT: s_waitcnt lgkmcnt(0)
221+
; GFX940-NEXT: v_mov_b32_e32 v3, v2
222+
; GFX940-NEXT: v_pk_add_f16 v2, v3, v1
223+
; GFX940-NEXT: ds_cmpst_rtn_b32 v2, v0, v3, v2 offset:65532
224+
; GFX940-NEXT: s_waitcnt lgkmcnt(0)
225+
; GFX940-NEXT: v_cmp_eq_u32_e32 vcc, v2, v3
226+
; GFX940-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
227+
; GFX940-NEXT: s_andn2_b64 exec, exec, s[0:1]
228+
; GFX940-NEXT: s_cbranch_execnz .LBB15_1
229+
; GFX940-NEXT: ; %bb.2: ; %atomicrmw.end
230+
; GFX940-NEXT: s_or_b64 exec, exec, s[0:1]
231+
; GFX940-NEXT: v_mov_b32_e32 v0, v2
232+
; GFX940-NEXT: s_setpc_b64 s[30:31]
233+
%gep = getelementptr <2 x half>, ptr addrspace(3) %ptr, i32 16383
234+
%result = atomicrmw fadd ptr addrspace(3) %gep, <2 x half> %val seq_cst
235+
ret <2 x half> %result
236+
}
237+
238+
define void @local_atomic_fadd_noret_v2f16_offset(ptr addrspace(3) %ptr, <2 x half> %val) {
239+
; GFX940-LABEL: local_atomic_fadd_noret_v2f16_offset:
240+
; GFX940: ; %bb.0:
241+
; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
242+
; GFX940-NEXT: ds_read_b32 v2, v0 offset:65532
243+
; GFX940-NEXT: s_mov_b64 s[0:1], 0
244+
; GFX940-NEXT: .LBB16_1: ; %atomicrmw.start
245+
; GFX940-NEXT: ; =>This Inner Loop Header: Depth=1
246+
; GFX940-NEXT: s_waitcnt lgkmcnt(0)
247+
; GFX940-NEXT: v_pk_add_f16 v3, v2, v1
248+
; GFX940-NEXT: ds_cmpst_rtn_b32 v3, v0, v2, v3 offset:65532
249+
; GFX940-NEXT: s_waitcnt lgkmcnt(0)
250+
; GFX940-NEXT: v_cmp_eq_u32_e32 vcc, v3, v2
251+
; GFX940-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
252+
; GFX940-NEXT: v_mov_b32_e32 v2, v3
253+
; GFX940-NEXT: s_andn2_b64 exec, exec, s[0:1]
254+
; GFX940-NEXT: s_cbranch_execnz .LBB16_1
255+
; GFX940-NEXT: ; %bb.2: ; %atomicrmw.end
256+
; GFX940-NEXT: s_or_b64 exec, exec, s[0:1]
257+
; GFX940-NEXT: s_setpc_b64 s[30:31]
258+
%gep = getelementptr <2 x half>, ptr addrspace(3) %ptr, i32 16383
259+
%unused = atomicrmw fadd ptr addrspace(3) %gep, <2 x half> %val seq_cst
260+
ret void
261+
}
262+
263+
define <2 x half> @global_atomic_fadd_ret_v2f16_agent_offset(ptr addrspace(1) %ptr, <2 x half> %val) {
264+
; GFX940-LABEL: global_atomic_fadd_ret_v2f16_agent_offset:
265+
; GFX940: ; %bb.0:
266+
; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
267+
; GFX940-NEXT: global_load_dword v3, v[0:1], off offset:1024
268+
; GFX940-NEXT: s_mov_b64 s[0:1], 0
269+
; GFX940-NEXT: .LBB17_1: ; %atomicrmw.start
270+
; GFX940-NEXT: ; =>This Inner Loop Header: Depth=1
271+
; GFX940-NEXT: s_waitcnt vmcnt(0)
272+
; GFX940-NEXT: v_mov_b32_e32 v5, v3
273+
; GFX940-NEXT: v_pk_add_f16 v4, v5, v2
274+
; GFX940-NEXT: buffer_wbl2 sc1
275+
; GFX940-NEXT: global_atomic_cmpswap v3, v[0:1], v[4:5], off offset:1024 sc0
276+
; GFX940-NEXT: s_waitcnt vmcnt(0)
277+
; GFX940-NEXT: buffer_inv sc1
278+
; GFX940-NEXT: v_cmp_eq_u32_e32 vcc, v3, v5
279+
; GFX940-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
280+
; GFX940-NEXT: s_andn2_b64 exec, exec, s[0:1]
281+
; GFX940-NEXT: s_cbranch_execnz .LBB17_1
282+
; GFX940-NEXT: ; %bb.2: ; %atomicrmw.end
283+
; GFX940-NEXT: s_or_b64 exec, exec, s[0:1]
284+
; GFX940-NEXT: v_mov_b32_e32 v0, v3
285+
; GFX940-NEXT: s_setpc_b64 s[30:31]
286+
%gep = getelementptr <2 x half>, ptr addrspace(1) %ptr, i32 256
287+
%result = atomicrmw fadd ptr addrspace(1) %gep, <2 x half> %val syncscope("agent") seq_cst
288+
ret <2 x half> %result
289+
}
290+
291+
define void @global_atomic_fadd_noret_v2f16_agent_offset(ptr addrspace(1) %ptr, <2 x half> %val) {
292+
; GFX940-LABEL: global_atomic_fadd_noret_v2f16_agent_offset:
293+
; GFX940: ; %bb.0:
294+
; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
295+
; GFX940-NEXT: global_load_dword v5, v[0:1], off offset:1024
296+
; GFX940-NEXT: s_mov_b64 s[0:1], 0
297+
; GFX940-NEXT: .LBB18_1: ; %atomicrmw.start
298+
; GFX940-NEXT: ; =>This Inner Loop Header: Depth=1
299+
; GFX940-NEXT: s_waitcnt vmcnt(0)
300+
; GFX940-NEXT: v_pk_add_f16 v4, v5, v2
301+
; GFX940-NEXT: buffer_wbl2 sc1
302+
; GFX940-NEXT: global_atomic_cmpswap v3, v[0:1], v[4:5], off offset:1024 sc0
303+
; GFX940-NEXT: s_waitcnt vmcnt(0)
304+
; GFX940-NEXT: buffer_inv sc1
305+
; GFX940-NEXT: v_cmp_eq_u32_e32 vcc, v3, v5
306+
; GFX940-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
307+
; GFX940-NEXT: v_mov_b32_e32 v5, v3
308+
; GFX940-NEXT: s_andn2_b64 exec, exec, s[0:1]
309+
; GFX940-NEXT: s_cbranch_execnz .LBB18_1
310+
; GFX940-NEXT: ; %bb.2: ; %atomicrmw.end
311+
; GFX940-NEXT: s_or_b64 exec, exec, s[0:1]
312+
; GFX940-NEXT: s_setpc_b64 s[30:31]
313+
%gep = getelementptr <2 x half>, ptr addrspace(1) %ptr, i32 256
314+
%unused = atomicrmw fadd ptr addrspace(1) %gep, <2 x half> %val syncscope("agent") seq_cst
315+
ret void
316+
}
317+
318+
define <2 x half> @flat_atomic_fadd_ret_v2f16_agent_offset(ptr %ptr, <2 x half> %val) {
319+
; GFX940-LABEL: flat_atomic_fadd_ret_v2f16_agent_offset:
320+
; GFX940: ; %bb.0:
321+
; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
322+
; GFX940-NEXT: flat_load_dword v3, v[0:1] offset:1024
323+
; GFX940-NEXT: s_mov_b64 s[0:1], 0
324+
; GFX940-NEXT: .LBB19_1: ; %atomicrmw.start
325+
; GFX940-NEXT: ; =>This Inner Loop Header: Depth=1
326+
; GFX940-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
327+
; GFX940-NEXT: v_mov_b32_e32 v5, v3
328+
; GFX940-NEXT: v_pk_add_f16 v4, v5, v2
329+
; GFX940-NEXT: buffer_wbl2 sc1
330+
; GFX940-NEXT: flat_atomic_cmpswap v3, v[0:1], v[4:5] offset:1024 sc0
331+
; GFX940-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
332+
; GFX940-NEXT: buffer_inv sc1
333+
; GFX940-NEXT: v_cmp_eq_u32_e32 vcc, v3, v5
334+
; GFX940-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
335+
; GFX940-NEXT: s_andn2_b64 exec, exec, s[0:1]
336+
; GFX940-NEXT: s_cbranch_execnz .LBB19_1
337+
; GFX940-NEXT: ; %bb.2: ; %atomicrmw.end
338+
; GFX940-NEXT: s_or_b64 exec, exec, s[0:1]
339+
; GFX940-NEXT: v_mov_b32_e32 v0, v3
340+
; GFX940-NEXT: s_setpc_b64 s[30:31]
341+
%gep = getelementptr <2 x half>, ptr %ptr, i32 256
342+
%result = atomicrmw fadd ptr %gep, <2 x half> %val syncscope("agent") seq_cst
343+
ret <2 x half> %result
344+
}
345+
346+
define void @flat_atomic_fadd_noret_v2f16_agent_offset(ptr %ptr, <2 x half> %val) {
347+
; GFX940-LABEL: flat_atomic_fadd_noret_v2f16_agent_offset:
348+
; GFX940: ; %bb.0:
349+
; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
350+
; GFX940-NEXT: flat_load_dword v5, v[0:1] offset:1024
351+
; GFX940-NEXT: s_mov_b64 s[0:1], 0
352+
; GFX940-NEXT: .LBB20_1: ; %atomicrmw.start
353+
; GFX940-NEXT: ; =>This Inner Loop Header: Depth=1
354+
; GFX940-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
355+
; GFX940-NEXT: v_pk_add_f16 v4, v5, v2
356+
; GFX940-NEXT: buffer_wbl2 sc1
357+
; GFX940-NEXT: flat_atomic_cmpswap v3, v[0:1], v[4:5] offset:1024 sc0
358+
; GFX940-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
359+
; GFX940-NEXT: buffer_inv sc1
360+
; GFX940-NEXT: v_cmp_eq_u32_e32 vcc, v3, v5
361+
; GFX940-NEXT: s_or_b64 s[0:1], vcc, s[0:1]
362+
; GFX940-NEXT: v_mov_b32_e32 v5, v3
363+
; GFX940-NEXT: s_andn2_b64 exec, exec, s[0:1]
364+
; GFX940-NEXT: s_cbranch_execnz .LBB20_1
365+
; GFX940-NEXT: ; %bb.2: ; %atomicrmw.end
366+
; GFX940-NEXT: s_or_b64 exec, exec, s[0:1]
367+
; GFX940-NEXT: s_setpc_b64 s[30:31]
368+
%gep = getelementptr <2 x half>, ptr %ptr, i32 256
369+
%unused = atomicrmw fadd ptr %gep, <2 x half> %val syncscope("agent") seq_cst
370+
ret void
371+
}
372+
212373
attributes #0 = { "denormal-fp-math-f32"="ieee,ieee" }

‎llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll

Lines changed: 157 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=fiji -O0 -stop-after=irtranslator -o - %s | FileCheck %s
2+
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx940 -O0 -stop-after=irtranslator -o - %s | FileCheck %s
33

44
define float @test_atomicrmw_fadd(ptr addrspace(3) %addr) {
55
; CHECK-LABEL: name: test_atomicrmw_fadd
@@ -34,20 +34,172 @@ define float @test_atomicrmw_fsub(ptr addrspace(3) %addr) {
3434
; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI [[LOAD]](s32), %bb.1, %13(s32), %bb.2
3535
; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[PHI1]], [[C]]
3636
; CHECK-NEXT: [[ATOMIC_CMPXCHG_WITH_SUCCESS:%[0-9]+]]:_(s32), [[ATOMIC_CMPXCHG_WITH_SUCCESS1:%[0-9]+]]:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[COPY]](p3), [[PHI1]], [[FSUB]] :: (load store seq_cst seq_cst (s32) on %ir.addr, addrspace 3)
37-
; CHECK-NEXT: [[INTRINSIC:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[ATOMIC_CMPXCHG_WITH_SUCCESS1]](s1), [[PHI]](s64)
38-
; CHECK-NEXT: [[INTRINSIC_W_SIDE_EFFECTS:%[0-9]+]]:_(s1) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.loop), [[INTRINSIC]](s64)
39-
; CHECK-NEXT: G_BRCOND [[INTRINSIC_W_SIDE_EFFECTS]](s1), %bb.3
37+
; CHECK-NEXT: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[ATOMIC_CMPXCHG_WITH_SUCCESS1]](s1), [[PHI]](s64)
38+
; CHECK-NEXT: [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.loop), [[INT]](s64)
39+
; CHECK-NEXT: G_BRCOND [[INT1]](s1), %bb.3
4040
; CHECK-NEXT: G_BR %bb.2
4141
; CHECK-NEXT: {{ $}}
4242
; CHECK-NEXT: bb.3.atomicrmw.end:
4343
; CHECK-NEXT: [[PHI2:%[0-9]+]]:_(s32) = G_PHI [[ATOMIC_CMPXCHG_WITH_SUCCESS]](s32), %bb.2
44-
; CHECK-NEXT: [[PHI3:%[0-9]+]]:_(s64) = G_PHI [[INTRINSIC]](s64), %bb.2
44+
; CHECK-NEXT: [[PHI3:%[0-9]+]]:_(s64) = G_PHI [[INT]](s64), %bb.2
4545
; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI3]](s64)
4646
; CHECK-NEXT: $vgpr0 = COPY [[PHI2]](s32)
4747
; CHECK-NEXT: SI_RETURN implicit $vgpr0
4848
%oldval = atomicrmw fsub ptr addrspace(3) %addr, float 1.0 seq_cst
4949
ret float %oldval
5050
}
5151

52+
define <2 x half> @test_atomicrmw_fadd_vector(ptr addrspace(3) %addr) {
53+
; CHECK-LABEL: name: test_atomicrmw_fadd_vector
54+
; CHECK: bb.1 (%ir-block.0):
55+
; CHECK-NEXT: successors: %bb.2(0x80000000)
56+
; CHECK-NEXT: liveins: $vgpr0
57+
; CHECK-NEXT: {{ $}}
58+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
59+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
60+
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16)
61+
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
62+
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>) from %ir.addr, addrspace 3)
63+
; CHECK-NEXT: G_BR %bb.2
64+
; CHECK-NEXT: {{ $}}
65+
; CHECK-NEXT: bb.2.atomicrmw.start:
66+
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
67+
; CHECK-NEXT: {{ $}}
68+
; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s64) = G_PHI %19(s64), %bb.2, [[C1]](s64), %bb.1
69+
; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(<2 x s16>) = G_PHI [[LOAD]](<2 x s16>), %bb.1, %18(<2 x s16>), %bb.2
70+
; CHECK-NEXT: [[FADD:%[0-9]+]]:_(<2 x s16>) = G_FADD [[PHI1]], [[BUILD_VECTOR]]
71+
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[FADD]](<2 x s16>)
72+
; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[PHI1]](<2 x s16>)
73+
; CHECK-NEXT: [[ATOMIC_CMPXCHG_WITH_SUCCESS:%[0-9]+]]:_(s32), [[ATOMIC_CMPXCHG_WITH_SUCCESS1:%[0-9]+]]:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[COPY]](p3), [[BITCAST1]], [[BITCAST]] :: (load store seq_cst seq_cst (s32) on %ir.addr, addrspace 3)
74+
; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[ATOMIC_CMPXCHG_WITH_SUCCESS]](s32)
75+
; CHECK-NEXT: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[ATOMIC_CMPXCHG_WITH_SUCCESS1]](s1), [[PHI]](s64)
76+
; CHECK-NEXT: [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.loop), [[INT]](s64)
77+
; CHECK-NEXT: G_BRCOND [[INT1]](s1), %bb.3
78+
; CHECK-NEXT: G_BR %bb.2
79+
; CHECK-NEXT: {{ $}}
80+
; CHECK-NEXT: bb.3.atomicrmw.end:
81+
; CHECK-NEXT: [[PHI2:%[0-9]+]]:_(<2 x s16>) = G_PHI [[BITCAST2]](<2 x s16>), %bb.2
82+
; CHECK-NEXT: [[PHI3:%[0-9]+]]:_(s64) = G_PHI [[INT]](s64), %bb.2
83+
; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI3]](s64)
84+
; CHECK-NEXT: $vgpr0 = COPY [[PHI2]](<2 x s16>)
85+
; CHECK-NEXT: SI_RETURN implicit $vgpr0
86+
%oldval = atomicrmw fadd ptr addrspace(3) %addr, <2 x half> <half 1.0, half 1.0> seq_cst
87+
ret <2 x half> %oldval
88+
}
89+
90+
define <2 x half> @test_atomicrmw_fsub_vector(ptr addrspace(3) %addr) {
91+
; CHECK-LABEL: name: test_atomicrmw_fsub_vector
92+
; CHECK: bb.1 (%ir-block.0):
93+
; CHECK-NEXT: successors: %bb.2(0x80000000)
94+
; CHECK-NEXT: liveins: $vgpr0
95+
; CHECK-NEXT: {{ $}}
96+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
97+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
98+
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16)
99+
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
100+
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>) from %ir.addr, addrspace 3)
101+
; CHECK-NEXT: G_BR %bb.2
102+
; CHECK-NEXT: {{ $}}
103+
; CHECK-NEXT: bb.2.atomicrmw.start:
104+
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
105+
; CHECK-NEXT: {{ $}}
106+
; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s64) = G_PHI %19(s64), %bb.2, [[C1]](s64), %bb.1
107+
; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(<2 x s16>) = G_PHI [[LOAD]](<2 x s16>), %bb.1, %18(<2 x s16>), %bb.2
108+
; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(<2 x s16>) = G_FSUB [[PHI1]], [[BUILD_VECTOR]]
109+
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[FSUB]](<2 x s16>)
110+
; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[PHI1]](<2 x s16>)
111+
; CHECK-NEXT: [[ATOMIC_CMPXCHG_WITH_SUCCESS:%[0-9]+]]:_(s32), [[ATOMIC_CMPXCHG_WITH_SUCCESS1:%[0-9]+]]:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[COPY]](p3), [[BITCAST1]], [[BITCAST]] :: (load store seq_cst seq_cst (s32) on %ir.addr, addrspace 3)
112+
; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[ATOMIC_CMPXCHG_WITH_SUCCESS]](s32)
113+
; CHECK-NEXT: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[ATOMIC_CMPXCHG_WITH_SUCCESS1]](s1), [[PHI]](s64)
114+
; CHECK-NEXT: [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.loop), [[INT]](s64)
115+
; CHECK-NEXT: G_BRCOND [[INT1]](s1), %bb.3
116+
; CHECK-NEXT: G_BR %bb.2
117+
; CHECK-NEXT: {{ $}}
118+
; CHECK-NEXT: bb.3.atomicrmw.end:
119+
; CHECK-NEXT: [[PHI2:%[0-9]+]]:_(<2 x s16>) = G_PHI [[BITCAST2]](<2 x s16>), %bb.2
120+
; CHECK-NEXT: [[PHI3:%[0-9]+]]:_(s64) = G_PHI [[INT]](s64), %bb.2
121+
; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI3]](s64)
122+
; CHECK-NEXT: $vgpr0 = COPY [[PHI2]](<2 x s16>)
123+
; CHECK-NEXT: SI_RETURN implicit $vgpr0
124+
%oldval = atomicrmw fsub ptr addrspace(3) %addr, <2 x half> <half 1.0, half 1.0> seq_cst
125+
ret <2 x half> %oldval
126+
}
127+
128+
define <2 x half> @test_atomicrmw_fmin_vector(ptr addrspace(3) %addr) {
129+
; CHECK-LABEL: name: test_atomicrmw_fmin_vector
130+
; CHECK: bb.1 (%ir-block.0):
131+
; CHECK-NEXT: successors: %bb.2(0x80000000)
132+
; CHECK-NEXT: liveins: $vgpr0
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; CHECK-NEXT: {{ $}}
134+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
135+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
136+
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16)
137+
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
138+
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>) from %ir.addr, addrspace 3)
139+
; CHECK-NEXT: G_BR %bb.2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: bb.2.atomicrmw.start:
142+
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s64) = G_PHI %19(s64), %bb.2, [[C1]](s64), %bb.1
145+
; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(<2 x s16>) = G_PHI [[LOAD]](<2 x s16>), %bb.1, %18(<2 x s16>), %bb.2
146+
; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:_(<2 x s16>) = G_FMINNUM [[PHI1]], [[BUILD_VECTOR]]
147+
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[FMINNUM]](<2 x s16>)
148+
; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[PHI1]](<2 x s16>)
149+
; CHECK-NEXT: [[ATOMIC_CMPXCHG_WITH_SUCCESS:%[0-9]+]]:_(s32), [[ATOMIC_CMPXCHG_WITH_SUCCESS1:%[0-9]+]]:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[COPY]](p3), [[BITCAST1]], [[BITCAST]] :: (load store seq_cst seq_cst (s32) on %ir.addr, addrspace 3)
150+
; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[ATOMIC_CMPXCHG_WITH_SUCCESS]](s32)
151+
; CHECK-NEXT: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[ATOMIC_CMPXCHG_WITH_SUCCESS1]](s1), [[PHI]](s64)
152+
; CHECK-NEXT: [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.loop), [[INT]](s64)
153+
; CHECK-NEXT: G_BRCOND [[INT1]](s1), %bb.3
154+
; CHECK-NEXT: G_BR %bb.2
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; CHECK-NEXT: {{ $}}
156+
; CHECK-NEXT: bb.3.atomicrmw.end:
157+
; CHECK-NEXT: [[PHI2:%[0-9]+]]:_(<2 x s16>) = G_PHI [[BITCAST2]](<2 x s16>), %bb.2
158+
; CHECK-NEXT: [[PHI3:%[0-9]+]]:_(s64) = G_PHI [[INT]](s64), %bb.2
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; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI3]](s64)
160+
; CHECK-NEXT: $vgpr0 = COPY [[PHI2]](<2 x s16>)
161+
; CHECK-NEXT: SI_RETURN implicit $vgpr0
162+
%oldval = atomicrmw fmin ptr addrspace(3) %addr, <2 x half> <half 1.0, half 1.0> seq_cst
163+
ret <2 x half> %oldval
164+
}
165+
166+
define <2 x half> @test_atomicrmw_fmax_vector(ptr addrspace(3) %addr) {
167+
; CHECK-LABEL: name: test_atomicrmw_fmax_vector
168+
; CHECK: bb.1 (%ir-block.0):
169+
; CHECK-NEXT: successors: %bb.2(0x80000000)
170+
; CHECK-NEXT: liveins: $vgpr0
171+
; CHECK-NEXT: {{ $}}
172+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
173+
; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3C00
174+
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[C]](s16), [[C]](s16)
175+
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
176+
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<2 x s16>) = G_LOAD [[COPY]](p3) :: (load (<2 x s16>) from %ir.addr, addrspace 3)
177+
; CHECK-NEXT: G_BR %bb.2
178+
; CHECK-NEXT: {{ $}}
179+
; CHECK-NEXT: bb.2.atomicrmw.start:
180+
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
181+
; CHECK-NEXT: {{ $}}
182+
; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s64) = G_PHI %19(s64), %bb.2, [[C1]](s64), %bb.1
183+
; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(<2 x s16>) = G_PHI [[LOAD]](<2 x s16>), %bb.1, %18(<2 x s16>), %bb.2
184+
; CHECK-NEXT: [[FMAXNUM:%[0-9]+]]:_(<2 x s16>) = G_FMAXNUM [[PHI1]], [[BUILD_VECTOR]]
185+
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[FMAXNUM]](<2 x s16>)
186+
; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[PHI1]](<2 x s16>)
187+
; CHECK-NEXT: [[ATOMIC_CMPXCHG_WITH_SUCCESS:%[0-9]+]]:_(s32), [[ATOMIC_CMPXCHG_WITH_SUCCESS1:%[0-9]+]]:_(s1) = G_ATOMIC_CMPXCHG_WITH_SUCCESS [[COPY]](p3), [[BITCAST1]], [[BITCAST]] :: (load store seq_cst seq_cst (s32) on %ir.addr, addrspace 3)
188+
; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[ATOMIC_CMPXCHG_WITH_SUCCESS]](s32)
189+
; CHECK-NEXT: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[ATOMIC_CMPXCHG_WITH_SUCCESS1]](s1), [[PHI]](s64)
190+
; CHECK-NEXT: [[INT1:%[0-9]+]]:_(s1) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.loop), [[INT]](s64)
191+
; CHECK-NEXT: G_BRCOND [[INT1]](s1), %bb.3
192+
; CHECK-NEXT: G_BR %bb.2
193+
; CHECK-NEXT: {{ $}}
194+
; CHECK-NEXT: bb.3.atomicrmw.end:
195+
; CHECK-NEXT: [[PHI2:%[0-9]+]]:_(<2 x s16>) = G_PHI [[BITCAST2]](<2 x s16>), %bb.2
196+
; CHECK-NEXT: [[PHI3:%[0-9]+]]:_(s64) = G_PHI [[INT]](s64), %bb.2
197+
; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI3]](s64)
198+
; CHECK-NEXT: $vgpr0 = COPY [[PHI2]](<2 x s16>)
199+
; CHECK-NEXT: SI_RETURN implicit $vgpr0
200+
%oldval = atomicrmw fmax ptr addrspace(3) %addr, <2 x half> <half 1.0, half 1.0> seq_cst
201+
ret <2 x half> %oldval
202+
}
203+
52204
!llvm.module.flags = !{!0}
53205
!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}

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