[RISCV] Replace vmv.s.x -> vmv.v.i DAG combine with patterns. NFC

We can also remove the combine that reduces LMUL, since we've removed the LMUL
variants in #71501.

Author: lukel97

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -15223,9 +15223,7 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
         return Src.getOperand(0);
       // TODO: Use insert_subvector/extract_subvector to change widen/narrow?
     }
-    [[fallthrough]];
-  }
-  case RISCVISD::VMV_S_X_VL: {
+
     const MVT VT = N->getSimpleValueType(0);
     SDValue Passthru = N->getOperand(0);
     SDValue Scalar = N->getOperand(1);
@@ -15243,15 +15241,6 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
                            DAG.getConstant(0, DL, XLenVT));
       return Result;
     }
-
-    // We use a vmv.v.i if possible.  We limit this to LMUL1.  LMUL2 or
-    // higher would involve overly constraining the register allocator for
-    // no purpose.
-    if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Scalar);
-        Const && !Const->isZero() && isInt<5>(Const->getSExtValue()) &&
-        VT.bitsLE(getLMUL1VT(VT)) && Passthru.isUndef())
-      return DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VT, Passthru, Scalar, VL);
-
     break;
   }
   case ISD::INTRINSIC_VOID:

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

@@ -2758,11 +2758,27 @@ foreach mti = AllMasks in {
 
 // 16. Vector Permutation Instructions
 
+def simm5_nonzero : ImmLeaf<XLenVT, [{return Imm != 0 && isInt<5>(Imm);}]>;
+
 // 16.1. Integer Scalar Move Instructions
 // 16.4. Vector Register Gather Instruction
 foreach vti = AllIntegerVectors in {
   let Predicates = GetVTypePredicates<vti>.Predicates in {
     defvar isGroup = !isa<GroupVTypeInfo>(vti);
+
+    // Use vmv.v.i if we're inserting into undef and the scalar fits into simm5
+    // (and also isn't 0, since we could then just use x0)
+    defvar pseudoVIInstr = !if(isGroup,
+                               PseudoVMV_V_I_M1,
+                               !cast<Instruction>("PseudoVMV_V_I_" # vti.LMul.MX));
+    defvar pseudoVI = (pseudoVIInstr (IMPLICIT_DEF), simm5:$imm, GPR:$vl,
+                                     vti.Log2SEW, TU_MU);
+    def : Pat<(vti.Vector (riscv_vmv_s_x_vl (vti.Vector undef),
+                                            simm5_nonzero:$imm,
+                                            VLOpFrag)),
+              !if(isGroup, (INSERT_SUBREG (IMPLICIT_DEF), pseudoVI, sub_vrm1_0),
+                           pseudoVI)>;
+
     defvar merge = !if(isGroup,
                        (!cast<GroupVTypeInfo>(vti).VectorM1
                           (EXTRACT_SUBREG $merge, sub_vrm1_0)),
@@ -2776,7 +2792,6 @@ foreach vti = AllIntegerVectors in {
               !if(isGroup, (INSERT_SUBREG $merge, pseudoVMV, sub_vrm1_0),
                             pseudoVMV)>;
 
-
     def : Pat<(vti.Vector (riscv_vrgather_vv_vl vti.RegClass:$rs2,
                                                 vti.RegClass:$rs1,
                                                 vti.RegClass:$merge,