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[AArch64][GlobalISel] Support more legal types for EXTEND
Expand (s/z/any)ext instructions to be compatible with more types for GlobalISel. This patch mainly focuses on 64-bit and 128-bit vectors with element size of powers of 2. It also notably handles larger than legal vectors. Differential Revision: https://reviews.llvm.org/D157113
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-208
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11 files changed

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‎llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -375,6 +375,7 @@ class LegalizerHelper {
375375
LegalizeResult lowerFunnelShiftWithInverse(MachineInstr &MI);
376376
LegalizeResult lowerFunnelShiftAsShifts(MachineInstr &MI);
377377
LegalizeResult lowerFunnelShift(MachineInstr &MI);
378+
LegalizeResult lowerEXT(MachineInstr &MI);
378379
LegalizeResult lowerRotateWithReverseRotate(MachineInstr &MI);
379380
LegalizeResult lowerRotate(MachineInstr &MI);
380381

‎llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Lines changed: 46 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3601,6 +3601,10 @@ LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT LowerHintTy) {
36013601
return lowerMemCpyFamily(MI);
36023602
case G_MEMCPY_INLINE:
36033603
return lowerMemcpyInline(MI);
3604+
case G_ZEXT:
3605+
case G_SEXT:
3606+
case G_ANYEXT:
3607+
return lowerEXT(MI);
36043608
GISEL_VECREDUCE_CASES_NONSEQ
36053609
return lowerVectorReduction(MI);
36063610
}
@@ -5955,6 +5959,48 @@ LegalizerHelper::lowerFunnelShift(MachineInstr &MI) {
59555959
return Result;
59565960
}
59575961

5962+
LegalizerHelper::LegalizeResult LegalizerHelper::lowerEXT(MachineInstr &MI) {
5963+
auto [Dst, Src] = MI.getFirst2Regs();
5964+
LLT DstTy = MRI.getType(Dst);
5965+
LLT SrcTy = MRI.getType(Src);
5966+
5967+
uint32_t DstTySize = DstTy.getSizeInBits();
5968+
uint32_t DstTyScalarSize = DstTy.getScalarSizeInBits();
5969+
uint32_t SrcTyScalarSize = SrcTy.getScalarSizeInBits();
5970+
5971+
if (!isPowerOf2_32(DstTySize) || !isPowerOf2_32(DstTyScalarSize) ||
5972+
!isPowerOf2_32(SrcTyScalarSize))
5973+
return UnableToLegalize;
5974+
5975+
// The step between extend is too large, split it by creating an intermediate
5976+
// extend instruction
5977+
if (SrcTyScalarSize * 2 < DstTyScalarSize) {
5978+
LLT MidTy = SrcTy.changeElementSize(SrcTyScalarSize * 2);
5979+
// If the destination type is illegal, split it into multiple statements
5980+
// zext x -> zext(merge(zext(unmerge), zext(unmerge)))
5981+
auto NewExt = MIRBuilder.buildInstr(MI.getOpcode(), {MidTy}, {Src});
5982+
// Unmerge the vector
5983+
LLT EltTy = MidTy.changeElementCount(
5984+
MidTy.getElementCount().divideCoefficientBy(2));
5985+
auto UnmergeSrc = MIRBuilder.buildUnmerge(EltTy, NewExt);
5986+
5987+
// ZExt the vectors
5988+
LLT ZExtResTy = DstTy.changeElementCount(
5989+
DstTy.getElementCount().divideCoefficientBy(2));
5990+
auto ZExtRes1 = MIRBuilder.buildInstr(MI.getOpcode(), {ZExtResTy},
5991+
{UnmergeSrc.getReg(0)});
5992+
auto ZExtRes2 = MIRBuilder.buildInstr(MI.getOpcode(), {ZExtResTy},
5993+
{UnmergeSrc.getReg(1)});
5994+
5995+
// Merge the ending vectors
5996+
MIRBuilder.buildMergeLikeInstr(Dst, {ZExtRes1, ZExtRes2});
5997+
5998+
MI.eraseFromParent();
5999+
return Legalized;
6000+
}
6001+
return UnableToLegalize;
6002+
}
6003+
59586004
LegalizerHelper::LegalizeResult
59596005
LegalizerHelper::lowerRotateWithReverseRotate(MachineInstr &MI) {
59606006
auto [Dst, DstTy, Src, SrcTy, Amt, AmtTy] = MI.getFirst3RegLLTs();

‎llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

Lines changed: 19 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -491,14 +491,13 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
491491
auto ExtLegalFunc = [=](const LegalityQuery &Query) {
492492
unsigned DstSize = Query.Types[0].getSizeInBits();
493493

494-
if (DstSize == 128 && !Query.Types[0].isVector())
495-
return false; // Extending to a scalar s128 needs narrowing.
496-
497-
// Make sure that we have something that will fit in a register, and
498-
// make sure it's a power of 2.
499-
if (DstSize < 8 || DstSize > 128 || !isPowerOf2_32(DstSize))
494+
// Handle legal vectors using legalFor
495+
if (Query.Types[0].isVector())
500496
return false;
501497

498+
if (DstSize < 8 || DstSize >= 128 || !isPowerOf2_32(DstSize))
499+
return false; // Extending to a scalar s128 needs narrowing.
500+
502501
const LLT &SrcTy = Query.Types[1];
503502

504503
// Make sure we fit in a register otherwise. Don't bother checking that
@@ -512,7 +511,20 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
512511
};
513512
getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT})
514513
.legalIf(ExtLegalFunc)
515-
.clampScalar(0, s64, s64); // Just for s128, others are handled above.
514+
.legalFor({{v2s64, v2s32}, {v4s32, v4s16}, {v8s16, v8s8}})
515+
.clampScalar(0, s64, s64) // Just for s128, others are handled above.
516+
.moreElementsToNextPow2(1)
517+
.clampMaxNumElements(1, s8, 8)
518+
.clampMaxNumElements(1, s16, 4)
519+
.clampMaxNumElements(1, s32, 2)
520+
// Tries to convert a large EXTEND into two smaller EXTENDs
521+
.lowerIf([=](const LegalityQuery &Query) {
522+
return (Query.Types[0].getScalarSizeInBits() >
523+
Query.Types[1].getScalarSizeInBits() * 2) &&
524+
Query.Types[0].isVector() &&
525+
(Query.Types[1].getScalarSizeInBits() == 8 ||
526+
Query.Types[1].getScalarSizeInBits() == 16);
527+
});
516528

517529
getActionDefinitionsBuilder(G_TRUNC)
518530
.minScalarOrEltIf(

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -243,15 +243,15 @@ body: |
243243
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $b0
244244
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s8) = COPY $b1
245245
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s8) = COPY $b2
246-
; CHECK-NEXT: [[ANYEXT0:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY]](s8)
246+
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY]](s8)
247247
; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY1]](s8)
248248
; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY2]](s8)
249-
; CHECK-NEXT: [[IMPLICIT_DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
250-
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[ANYEXT0]](s16), [[ANYEXT1]](s16), [[ANYEXT2]](s16), [[IMPLICIT_DEF]](s16)
249+
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
250+
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[ANYEXT]](s16), [[ANYEXT1]](s16), [[ANYEXT2]](s16), [[DEF]](s16)
251251
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s16>) = G_AND [[BUILD_VECTOR]], [[BUILD_VECTOR]]
252-
; CHECK-NEXT: [[VAL0:%[0-9]+]]:_(s16), [[VAL1:%[0-9]+]]:_(s16), [[VAL2:%[0-9]+]]:_(s16), [[VAL3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[AND]](<4 x s16>)
253-
; CHECK-NEXT: [[TRUNC3:%[0-9]+]]:_(s8) = G_TRUNC [[VAL0]](s16)
254-
; CHECK-NEXT: $b0 = COPY [[TRUNC3]](s8)
252+
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[AND]](<4 x s16>)
253+
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[UV]](s16)
254+
; CHECK-NEXT: $b0 = COPY [[TRUNC]](s8)
255255
; CHECK-NEXT: RET_ReallyLR implicit $b0
256256
%1:_(s8) = COPY $b0
257257
%2:_(s8) = COPY $b1

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-build-vector.mir

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -129,8 +129,8 @@ body: |
129129
%0:_(s16) = COPY $h0
130130
%1:_(s16) = COPY $h1
131131
%2:_(<2 x s16>) = G_BUILD_VECTOR %0(s16), %1(s16)
132-
%ext:_(<2 x s32>) = G_ANYEXT %2(<2 x s16>)
133-
$d0 = COPY %ext(<2 x s32>)
132+
%3:_(<2 x s32>) = G_ANYEXT %2(<2 x s16>)
133+
$d0 = COPY %3(<2 x s32>)
134134
RET_ReallyLR
135135
...
136136

@@ -141,14 +141,14 @@ body: |
141141
; CHECK-LABEL: name: widen_v2s8
142142
; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
143143
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
144-
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[DEF]](s32)
145-
; CHECK-NEXT: $d0 = COPY [[BUILD_VECTOR]](<2 x s32>)
144+
; CHECK-NEXT: %3:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[DEF]](s32)
145+
; CHECK-NEXT: $d0 = COPY %3(<2 x s32>)
146146
; CHECK-NEXT: RET_ReallyLR
147147
%0:_(s8) = G_IMPLICIT_DEF
148148
%1:_(s8) = G_IMPLICIT_DEF
149149
%2:_(<2 x s8>) = G_BUILD_VECTOR %0(s8), %1(s8)
150-
%ext:_(<2 x s32>) = G_ANYEXT %2(<2 x s8>)
151-
$d0 = COPY %ext(<2 x s32>)
150+
%3:_(<2 x s32>) = G_ANYEXT %2(<2 x s8>)
151+
$d0 = COPY %3(<2 x s32>)
152152
RET_ReallyLR
153153
...
154154

@@ -169,7 +169,7 @@ body: |
169169
%2:_(s8) = G_IMPLICIT_DEF
170170
%3:_(s8) = G_IMPLICIT_DEF
171171
%4:_(<4 x s8>) = G_BUILD_VECTOR %0(s8), %1(s8), %2(s8), %3(s8)
172-
%ext:_(<4 x s16>) = G_ANYEXT %4(<4 x s8>)
173-
$d0 = COPY %ext(<4 x s16>)
172+
%5:_(<4 x s16>) = G_ANYEXT %4(<4 x s8>)
173+
$d0 = COPY %5(<4 x s16>)
174174
RET_ReallyLR
175175
...

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir

Lines changed: 9 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -274,13 +274,12 @@ body: |
274274
; CHECK-LABEL: name: test_uitofp_v2s64_v2i1
275275
; CHECK: liveins: $q0
276276
; CHECK-NEXT: {{ $}}
277-
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
278-
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
279-
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[DEF]](s32)
280277
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
281-
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
282-
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<2 x s64>) = G_ANYEXT [[BUILD_VECTOR]](<2 x s32>)
283-
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[ANYEXT]], [[BUILD_VECTOR1]]
278+
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
279+
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
280+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY [[DEF]](s64)
281+
; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[DEF]](s64), [[COPY]](s64)
282+
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[BUILD_VECTOR1]], [[BUILD_VECTOR]]
284283
; CHECK-NEXT: [[UITOFP:%[0-9]+]]:_(<2 x s64>) = G_UITOFP [[AND]](<2 x s64>)
285284
; CHECK-NEXT: $q0 = COPY [[UITOFP]](<2 x s64>)
286285
%0:_(<2 x s1>) = G_IMPLICIT_DEF
@@ -296,11 +295,10 @@ body: |
296295
; CHECK-LABEL: name: test_sitofp_v2s64_v2i1
297296
; CHECK: liveins: $q0
298297
; CHECK-NEXT: {{ $}}
299-
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
300-
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY [[DEF]](s32)
301-
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[DEF]](s32)
302-
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(<2 x s64>) = G_ANYEXT [[BUILD_VECTOR]](<2 x s32>)
303-
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[ANYEXT]], 1
298+
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
299+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY [[DEF]](s64)
300+
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[DEF]](s64), [[COPY]](s64)
301+
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(<2 x s64>) = G_SEXT_INREG [[BUILD_VECTOR]], 1
304302
; CHECK-NEXT: [[SITOFP:%[0-9]+]]:_(<2 x s64>) = G_SITOFP [[SEXT_INREG]](<2 x s64>)
305303
; CHECK-NEXT: $q0 = COPY [[SITOFP]](<2 x s64>)
306304
%0:_(<2 x s1>) = G_IMPLICIT_DEF

‎llvm/test/CodeGen/AArch64/aarch64-addv.ll

Lines changed: 64 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -69,14 +69,40 @@ define i64 @add_D(ptr %arr) {
6969
declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32>)
7070

7171
define i32 @oversized_ADDV_256(ptr noalias nocapture readonly %arg1, ptr noalias nocapture readonly %arg2) {
72-
; CHECK-LABEL: oversized_ADDV_256:
73-
; CHECK: // %bb.0: // %entry
74-
; CHECK-NEXT: ldr d0, [x0]
75-
; CHECK-NEXT: ldr d1, [x1]
76-
; CHECK-NEXT: uabdl v0.8h, v0.8b, v1.8b
77-
; CHECK-NEXT: uaddlv s0, v0.8h
78-
; CHECK-NEXT: fmov w0, s0
79-
; CHECK-NEXT: ret
72+
; SDAG-LABEL: oversized_ADDV_256:
73+
; SDAG: // %bb.0: // %entry
74+
; SDAG-NEXT: ldr d0, [x0]
75+
; SDAG-NEXT: ldr d1, [x1]
76+
; SDAG-NEXT: uabdl v0.8h, v0.8b, v1.8b
77+
; SDAG-NEXT: uaddlv s0, v0.8h
78+
; SDAG-NEXT: fmov w0, s0
79+
; SDAG-NEXT: ret
80+
;
81+
; GISEL-LABEL: oversized_ADDV_256:
82+
; GISEL: // %bb.0: // %entry
83+
; GISEL-NEXT: ldr d1, [x0]
84+
; GISEL-NEXT: ldr d2, [x1]
85+
; GISEL-NEXT: movi v0.2d, #0000000000000000
86+
; GISEL-NEXT: ushll v1.8h, v1.8b, #0
87+
; GISEL-NEXT: ushll v2.8h, v2.8b, #0
88+
; GISEL-NEXT: mov d3, v1.d[1]
89+
; GISEL-NEXT: mov d4, v2.d[1]
90+
; GISEL-NEXT: usubl v1.4s, v1.4h, v2.4h
91+
; GISEL-NEXT: usubl v2.4s, v3.4h, v4.4h
92+
; GISEL-NEXT: cmgt v3.4s, v0.4s, v1.4s
93+
; GISEL-NEXT: neg v4.4s, v1.4s
94+
; GISEL-NEXT: cmgt v0.4s, v0.4s, v2.4s
95+
; GISEL-NEXT: shl v3.4s, v3.4s, #31
96+
; GISEL-NEXT: shl v0.4s, v0.4s, #31
97+
; GISEL-NEXT: neg v5.4s, v2.4s
98+
; GISEL-NEXT: sshr v3.4s, v3.4s, #31
99+
; GISEL-NEXT: sshr v0.4s, v0.4s, #31
100+
; GISEL-NEXT: bit v1.16b, v4.16b, v3.16b
101+
; GISEL-NEXT: bsl v0.16b, v5.16b, v2.16b
102+
; GISEL-NEXT: add v0.4s, v1.4s, v0.4s
103+
; GISEL-NEXT: addv s0, v0.4s
104+
; GISEL-NEXT: fmov w0, s0
105+
; GISEL-NEXT: ret
80106
entry:
81107
%0 = load <8 x i8>, ptr %arg1, align 1
82108
%1 = zext <8 x i8> %0 to <8 x i32>
@@ -93,16 +119,16 @@ entry:
93119
declare i32 @llvm.vector.reduce.add.v16i32(<16 x i32>)
94120

95121
define i32 @oversized_ADDV_512(ptr %arr) {
96-
; SDAG-LABEL: oversized_ADDV_512:
97-
; SDAG: // %bb.0:
98-
; SDAG-NEXT: ldp q0, q1, [x0, #32]
99-
; SDAG-NEXT: ldp q3, q2, [x0]
100-
; SDAG-NEXT: add v0.4s, v3.4s, v0.4s
101-
; SDAG-NEXT: add v1.4s, v2.4s, v1.4s
102-
; SDAG-NEXT: add v0.4s, v0.4s, v1.4s
103-
; SDAG-NEXT: addv s0, v0.4s
104-
; SDAG-NEXT: fmov w0, s0
105-
; SDAG-NEXT: ret
122+
; SDAG-LABEL: oversized_ADDV_512:
123+
; SDAG: // %bb.0:
124+
; SDAG-NEXT: ldp q0, q1, [x0, #32]
125+
; SDAG-NEXT: ldp q3, q2, [x0]
126+
; SDAG-NEXT: add v0.4s, v3.4s, v0.4s
127+
; SDAG-NEXT: add v1.4s, v2.4s, v1.4s
128+
; SDAG-NEXT: add v0.4s, v0.4s, v1.4s
129+
; SDAG-NEXT: addv s0, v0.4s
130+
; SDAG-NEXT: fmov w0, s0
131+
; SDAG-NEXT: ret
106132
;
107133
; GISEL-LABEL: oversized_ADDV_512:
108134
; GISEL: // %bb.0:
@@ -148,19 +174,19 @@ entry:
148174
}
149175

150176
define i32 @addv_combine_i32(<4 x i32> %a1, <4 x i32> %a2) {
151-
; SDAG-LABEL: addv_combine_i32:
152-
; SDAG: // %bb.0: // %entry
153-
; SDAG-NEXT: add v0.4s, v0.4s, v1.4s
154-
; SDAG-NEXT: addv s0, v0.4s
155-
; SDAG-NEXT: fmov w0, s0
156-
; SDAG-NEXT: ret
177+
; SDAG-LABEL: addv_combine_i32:
178+
; SDAG: // %bb.0: // %entry
179+
; SDAG-NEXT: add v0.4s, v0.4s, v1.4s
180+
; SDAG-NEXT: addv s0, v0.4s
181+
; SDAG-NEXT: fmov w0, s0
182+
; SDAG-NEXT: ret
157183
;
158184
; GISEL-LABEL: addv_combine_i32:
159185
; GISEL: // %bb.0: // %entry
160-
; GISEL-NEXT: addv s0, v0.4s
161-
; GISEL-NEXT: addv s1, v1.4s
162-
; GISEL-NEXT: fmov w8, s0
163-
; GISEL-NEXT: fmov w9, s1
186+
; GISEL-NEXT: addv s0, v0.4s
187+
; GISEL-NEXT: addv s1, v1.4s
188+
; GISEL-NEXT: fmov w8, s0
189+
; GISEL-NEXT: fmov w9, s1
164190
; GISEL-NEXT: add w0, w8, w9
165191
; GISEL-NEXT: ret
166192
entry:
@@ -171,19 +197,19 @@ entry:
171197
}
172198

173199
define i64 @addv_combine_i64(<2 x i64> %a1, <2 x i64> %a2) {
174-
; SDAG-LABEL: addv_combine_i64:
175-
; SDAG: // %bb.0: // %entry
176-
; SDAG-NEXT: add v0.2d, v0.2d, v1.2d
177-
; SDAG-NEXT: addp d0, v0.2d
178-
; SDAG-NEXT: fmov x0, d0
179-
; SDAG-NEXT: ret
200+
; SDAG-LABEL: addv_combine_i64:
201+
; SDAG: // %bb.0: // %entry
202+
; SDAG-NEXT: add v0.2d, v0.2d, v1.2d
203+
; SDAG-NEXT: addp d0, v0.2d
204+
; SDAG-NEXT: fmov x0, d0
205+
; SDAG-NEXT: ret
180206
;
181207
; GISEL-LABEL: addv_combine_i64:
182208
; GISEL: // %bb.0: // %entry
183-
; GISEL-NEXT: addp d0, v0.2d
184-
; GISEL-NEXT: addp d1, v1.2d
185-
; GISEL-NEXT: fmov x8, d0
186-
; GISEL-NEXT: fmov x9, d1
209+
; GISEL-NEXT: addp d0, v0.2d
210+
; GISEL-NEXT: addp d1, v1.2d
211+
; GISEL-NEXT: fmov x8, d0
212+
; GISEL-NEXT: fmov x9, d1
187213
; GISEL-NEXT: add x0, x8, x9
188214
; GISEL-NEXT: ret
189215
entry:

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