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[PowerPC][LLC] Utilize PPC::getNormalizedPPCTargetCPU() to set CPU (#113943)
Utilize common API in PPCTargetParser (#97541) to set default CPU with same interfaces for LLC. This will update AIX default CPU to pwr7 and LoP powerppc64 default CPU to ppc64.
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‎llvm/docs/ReleaseNotes.md

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@@ -164,6 +164,9 @@ Changes to the MIPS Backend
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Changes to the PowerPC Backend
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------------------------------
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* The Linux `ppc64` LLC default cpu is updated from `ppc` to `ppc64`.
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* The AIX LLC default cpu is updated from `generic` to `pwr7`.
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Changes to the RISC-V Backend
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-----------------------------
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‎llvm/lib/Target/PowerPC/PPCSubtarget.cpp

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@@ -29,6 +29,7 @@
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/TargetParser/PPCTargetParser.h"
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#include <cstdlib>
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using namespace llvm;
@@ -79,13 +80,10 @@ void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef TuneCPU,
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// Determine default and user specified characteristics
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std::string CPUName = std::string(CPU);
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if (CPUName.empty() || CPU == "generic") {
82-
// If cross-compiling with -march=ppc64le without -mcpu
83-
if (TargetTriple.getArch() == Triple::ppc64le)
84-
CPUName = "ppc64le";
85-
else if (TargetTriple.getSubArch() == Triple::PPCSubArch_spe)
83+
if (TargetTriple.getSubArch() == Triple::PPCSubArch_spe)
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CPUName = "e500";
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else
88-
CPUName = "generic";
86+
CPUName = std::string(PPC::getNormalizedPPCTargetCPU(TargetTriple));
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}
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// Determine the CPU to schedule for.

‎llvm/test/Analysis/LoopCacheAnalysis/PowerPC/compute-cost-m32.ll

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@@ -6,7 +6,7 @@ target triple = "powerpc-ibm-aix7.2.0.0"
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; Check IndexedReference::computeRefCost can handle type differences between
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; CacheLineSize and Numerator
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9-
; CHECK: Loop '_loop_1_do_' has cost = 2
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; CHECK: Loop '_loop_1_do_' has cost = 1
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%_elem_type_of_v = type <{ i32 }>
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‎llvm/test/CodeGen/PowerPC/2007-11-16-landingpad-split.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s
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; RUN: llc -mcpu=ppc -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck %s
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;; Formerly crashed, see PR 1508
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
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target triple = "powerpc64-unknown-linux-gnu"

‎llvm/test/CodeGen/PowerPC/Frames-dyn-alloca.ll

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@@ -1,7 +1,7 @@
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; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu | FileCheck %s -check-prefix=PPC32-LINUX
2-
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s -check-prefix=PPC64-LINUX
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; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=ppc | FileCheck %s -check-prefix=PPC64-LINUX
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; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -frame-pointer=all | FileCheck %s -check-prefix=PPC32-LINUX
4-
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -frame-pointer=all | FileCheck %s -check-prefix=PPC64-LINUX
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; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=ppc -frame-pointer=all | FileCheck %s -check-prefix=PPC64-LINUX
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; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu | FileCheck %s -check-prefix=PPC32-LINUX
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; RUN: llc < %s -mcpu=pwr4 -mattr=-altivec -verify-machineinstrs \

‎llvm/test/CodeGen/PowerPC/Frames-large.ll

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; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu \
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; RUN: -frame-pointer=all | FileCheck %s -check-prefix=PPC32-LINUX-FP
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7-
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu | \
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; RUN: llc -verify-machineinstrs < %s -mcpu=ppc -mtriple=powerpc64-unknown-linux-gnu | \
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; RUN: FileCheck %s -check-prefix=PPC64-LINUX-NOFP
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10-
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: llc -verify-machineinstrs < %s -mcpu=ppc -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -frame-pointer=all | FileCheck %s -check-prefix=PPC64-LINUX-FP
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; RUN: llc -verify-machineinstrs < %s -mcpu=pwr4 -mattr=-altivec \

‎llvm/test/CodeGen/PowerPC/P10-stack-alignment.ll

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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s --check-prefix=CHECK-LE
5-
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: llc -verify-machineinstrs -mcpu=ppc -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
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; RUN: FileCheck %s --check-prefix=CHECK-BE
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; RUN: opt --passes='sroa,loop-vectorize,loop-unroll,instcombine' -S \

‎llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll

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; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
2-
; RUN: llc -mtriple powerpc-ibm-aix-xcoff -stop-after=machine-cp -verify-machineinstrs < %s | \
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; RUN: llc -mtriple powerpc-ibm-aix-xcoff -mcpu=ppc -stop-after=machine-cp -verify-machineinstrs < %s | \
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; RUN: FileCheck --check-prefix=32BIT %s
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5-
; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -stop-after=machine-cp -verify-machineinstrs < %s | \
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; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -mcpu=ppc -stop-after=machine-cp -verify-machineinstrs < %s | \
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; RUN: FileCheck --check-prefix=64BIT %s
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define void @call_test_chars() {

‎llvm/test/CodeGen/PowerPC/aix-dwarf.ll

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@@ -1,9 +1,9 @@
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2-
; RUN: llc -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
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; RUN: llc -mtriple powerpc-ibm-aix-xcoff -mcpu=ppc -filetype=obj -o %t.o < %s
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; RUN: llvm-readobj --section-headers %t.o | FileCheck %s --check-prefixes=SEC,SEC32
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; RUN: llvm-objdump -r %t.o | FileCheck %s --check-prefix=RELO
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6-
; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -filetype=obj -o %t64.o < %s
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; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -mcpu=ppc -filetype=obj -o %t64.o < %s
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; RUN: llvm-readobj --section-headers %t64.o | FileCheck %s --check-prefixes=SEC,SEC64
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; RUN: llvm-objdump -r %t64.o | FileCheck %s --check-prefix=RELO64
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‎llvm/test/CodeGen/PowerPC/aix-static-init-non-default-priority.ll

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@@ -1,5 +1,5 @@
1-
; RUN: llc -mtriple powerpc-ibm-aix-xcoff -verify-machineinstrs < %s | FileCheck %s
2-
; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -verify-machineinstrs < %s | FileCheck %s
1+
; RUN: llc -mtriple powerpc-ibm-aix-xcoff -mcpu=ppc -verify-machineinstrs < %s | FileCheck %s
2+
; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -mcpu=ppc -verify-machineinstrs < %s | FileCheck %s
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@llvm.global_ctors = appending global [5 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 0, ptr @cf1, ptr null }, { i32, ptr, ptr } { i32 21, ptr @cf2, ptr null }, { i32, ptr, ptr } { i32 81, ptr @cf3, ptr null }, { i32, ptr, ptr } { i32 1125, ptr @cf4, ptr null }, { i32, ptr, ptr } { i32 64512, ptr @cf5, ptr null }]
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@llvm.global_dtors = appending global [5 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 20, ptr @df1, ptr null }, { i32, ptr, ptr } { i32 80, ptr @df2, ptr null }, { i32, ptr, ptr } { i32 1124, ptr @df3, ptr null }, { i32, ptr, ptr } { i32 64511, ptr @df4, ptr null }, { i32, ptr, ptr } { i32 65535, ptr @df5, ptr null }]

‎llvm/test/CodeGen/PowerPC/aix-weak-reloc.ll

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1-
; RUN: llc -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s
1+
; RUN: llc -mtriple powerpc-ibm-aix-xcoff -mcpu=ppc -filetype=obj -o %t.o < %s
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; RUN: llvm-objdump -dr %t.o | FileCheck --check-prefix=OBJ32 %s
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4-
; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -filetype=obj -o %t.o < %s
4+
; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -mcpu=ppc -filetype=obj -o %t.o < %s
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; RUN: llvm-objdump -dr %t.o | FileCheck --check-prefix=OBJ64 %s
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; Function Attrs: noinline nounwind optnone

‎llvm/test/CodeGen/PowerPC/aix-xcoff-exception-section-debug.ll

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; This file contains exception section testing for when debug information is present.
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; The 32-bit test should not print exception auxilliary entries because they are a 64-bit only feature.
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; Exception auxilliary entries are present in the 64-bit tests because 64-bit && debug enabled are the requirements.
4-
; RUN: llc -mtriple=powerpc-ibm-aix-xcoff -filetype=obj -o %t_32.o < %s
4+
; RUN: llc -mtriple=powerpc-ibm-aix-xcoff -mcpu=ppc -filetype=obj -o %t_32.o < %s
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; RUN: llvm-readobj --syms %t_32.o | FileCheck %s --check-prefix=SYMS32
6-
; RUN: llc -mtriple=powerpc64-unknown-aix -filetype=obj -o %t_32.o < %s
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; RUN: llc -mtriple=powerpc64-unknown-aix -mcpu=ppc -filetype=obj -o %t_32.o < %s
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; RUN: llvm-readobj --syms %t_32.o | FileCheck %s --check-prefix=SYMS64
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; If any debug information is included in a module and is XCOFF64, exception auxilliary entries are emitted

‎llvm/test/CodeGen/PowerPC/aix-xcoff-exception-section.ll

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; Testing 32-bit and 64-bit exception section entries, no exception auxilliary
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; entries should be produced as no debug information is specified.
3-
; RUN: llc -mtriple=powerpc-ibm-aix-xcoff -filetype=obj -o %t_32.o < %s
3+
; RUN: llc -mtriple=powerpc-ibm-aix-xcoff -mcpu=ppc -filetype=obj -o %t_32.o < %s
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; RUN: llvm-readobj --exception-section %t_32.o | FileCheck %s --check-prefix=EXCEPT
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; RUN: llvm-readobj --section-headers %t_32.o | FileCheck %s --check-prefix=READ
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; RUN: llvm-readobj --syms %t_32.o | FileCheck %s --check-prefix=SYMS
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8-
; RUN: llc -mtriple=powerpc64-unknown-aix -filetype=obj -o %t_64.o < %s
8+
; RUN: llc -mtriple=powerpc64-unknown-aix -mcpu=ppc -filetype=obj -o %t_64.o < %s
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; RUN: llvm-readobj --exception-section %t_64.o | FileCheck %s --check-prefix=EXCEPT64
1010
; RUN: llvm-readobj --section-headers %t_64.o | FileCheck %s --check-prefix=READ64
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; RUN: llvm-readobj --syms %t_64.o | FileCheck %s --check-prefix=SYMS64

‎llvm/test/CodeGen/PowerPC/aix-xcoff-visibility.ll

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; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr4 -mattr=-altivec -data-sections=false < %s |\
44
; RUN: FileCheck %s
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6-
; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -filetype=obj %s -o %t.o
6+
; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=ppc -filetype=obj %s -o %t.o
77
; RUN: llvm-readobj --syms --auxiliary-header %t.o | FileCheck %s --check-prefixes=SYM,AUX32
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9-
; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -filetype=obj %s -o %t64.o
9+
; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=ppc -filetype=obj %s -o %t64.o
1010
; RUN: llvm-readobj --syms --auxiliary-header %t64.o | FileCheck %s --check-prefixes=SYM,AUX64
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1212
@b = global i32 0, align 4

‎llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O2 -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck --check-prefix=ASM32 %s
3-
; RUN: llc -O2 -mtriple powerpc-ibm-aix-xcoff -stop-after=machine-cp -verify-machineinstrs < %s | FileCheck --check-prefix=32BIT %s
3+
; RUN: llc -O2 -mtriple powerpc-ibm-aix-xcoff -mcpu=ppc -stop-after=machine-cp -verify-machineinstrs < %s | FileCheck --check-prefix=32BIT %s
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55
define i32 @int_va_arg(i32 %a, ...) local_unnamed_addr {
66
; ASM32-LABEL: int_va_arg:

‎llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg.ll

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@@ -1,4 +1,4 @@
1-
; RUN: llc -O2 -mtriple powerpc64-ibm-aix-xcoff -stop-after=machine-cp -verify-machineinstrs < %s | \
1+
; RUN: llc -O2 -mtriple powerpc64-ibm-aix-xcoff -mcpu=ppc -stop-after=machine-cp -verify-machineinstrs < %s | \
22
; RUN: FileCheck --check-prefix=64BIT %s
33

44
; RUN: llc -O2 -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec \

‎llvm/test/CodeGen/PowerPC/aix64-csr-alloc.mir

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# REQUIRES: asserts
22
# RUN: llc -verify-machineinstrs -simplify-mir -mtriple=powerpc64-ibm-aix-xcoff \
3-
# RUN: -debug-only=regalloc %s -o - 2>&1 | FileCheck %s
3+
# RUN: -mcpu=ppc -debug-only=regalloc %s -o - 2>&1 | FileCheck %s
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55
---
66
name: i64
@@ -19,4 +19,4 @@ body: |
1919
# CHECK-DAG: AllocationOrder(VFRC) = [ $vf2 $vf3 $vf4 $vf5 $vf0 $vf1 $vf6 $vf7 $vf8 $vf9 $vf10 $vf11 $vf12 $vf13 $vf14 $vf15 $vf16 $vf17 $vf18 $vf19 $vf31 $vf30 $vf29 $vf28 $vf27 $vf26 $vf25 $vf24 $vf23 $vf22 $vf21 $vf20 ]
2020
# CHECK-DAG: AllocationOrder(G8RC_and_G8RC_NOX0) = [ $x3 $x4 $x5 $x6 $x7 $x8 $x9 $x10 $x11 $x12 $x31 $x30 $x29 $x28 $x27 $x26 $x25 $x24 $x23 $x22 $x21 $x20 $x19 $x18 $x17 $x16 $x15 $x1
2121
# CHECK-DAG: 4 ]
22-
# CHECK-DAG: AllocationOrder(F8RC) = [ $f0 $f1 $f2 $f3 $f4 $f5 $f6 $f7 $f8 $f9 $f10 $f11 $f12 $f13 $f31 $f30 $f29 $f28 $f27 $f26 $f25 $f24 $f23 $f22 $f21 $f20 $f19 $f18 $f17 $f16 $f15 $f14 ]
22+
# CHECK-DAG: AllocationOrder(F8RC) = [ $f0 $f1 $f2 $f3 $f4 $f5 $f6 $f7 $f8 $f9 $f10 $f11 $f12 $f13 $f31 $f30 $f29 $f28 $f27 $f26 $f25 $f24 $f23 $f22 $f21 $f20 $f19 $f18 $f17 $f16 $f15 $f14 ]

‎llvm/test/CodeGen/PowerPC/alloca-oversized.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
2-
; RUN: llc < %s -mtriple=powerpc-ibm-aix-xcoff | FileCheck %s
2+
; RUN: llc < %s -mcpu=ppc -mtriple=powerpc-ibm-aix-xcoff | FileCheck %s
33
define void @test_oversized(ptr %dst, i32 %cond) {
44
; CHECK-LABEL: test_oversized:
55
; CHECK: # %bb.0: # %entry

‎llvm/test/CodeGen/PowerPC/atomic-float.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
2+
; RUN: llc -verify-machineinstrs -mcpu=ppc -mtriple=powerpc64-unknown-unknown \
33
; RUN: < %s | FileCheck --check-prefix=CHECK-64 %s
4-
; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-unknown \
4+
; RUN: llc -verify-machineinstrs -mcpu=ppc -mtriple=powerpc-unknown-unknown \
55
; RUN: < %s | FileCheck --check-prefix=CHECK-32 %s
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define float @test_add(ptr %ptr, float %incr) {

‎llvm/test/CodeGen/PowerPC/atomicrmw-cond-sub-clamp.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
2+
; RUN: llc -mcpu=ppc -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
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44
define i8 @atomicrmw_usub_cond_i8(ptr %ptr, i8 %val) {
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; CHECK-LABEL: atomicrmw_usub_cond_i8:

‎llvm/test/CodeGen/PowerPC/atomicrmw-uinc-udec-wrap.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
2+
; RUN: llc -mcpu=ppc -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
33

44
define i8 @atomicrmw_uinc_wrap_i8(ptr %ptr, i8 %val) {
55
; CHECK-LABEL: atomicrmw_uinc_wrap_i8:

‎llvm/test/CodeGen/PowerPC/atomics-indexed.ll

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; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -verify-machineinstrs -ppc-asm-full-reg-names | FileCheck %s --check-prefix=CHECK --check-prefix=PPC32
33
; FIXME: -verify-machineinstrs currently fail on ppc64 (mismatched register/instruction).
44
; This is already checked for in Atomics-64.ll
5-
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -ppc-asm-full-reg-names | FileCheck %s --check-prefix=CHECK --check-prefix=PPC64
5+
; RUN: llc < %s -mcpu=ppc -mtriple=powerpc64-unknown-linux-gnu -ppc-asm-full-reg-names | FileCheck %s --check-prefix=CHECK --check-prefix=PPC64
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; In this file, we check that atomic load/store can make use of the indexed
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; versions of the instructions.

‎llvm/test/CodeGen/PowerPC/atomics.ll

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu -verify-machineinstrs -ppc-asm-full-reg-names | FileCheck %s --check-prefix=CHECK --check-prefix=PPC32
33
; This is already checked for in Atomics-64.ll
4-
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -ppc-asm-full-reg-names | FileCheck %s --check-prefix=CHECK --check-prefix=PPC64
4+
; RUN: llc -verify-machineinstrs < %s -mcpu=ppc -mtriple=powerpc64-unknown-linux-gnu -ppc-asm-full-reg-names | FileCheck %s --check-prefix=CHECK --check-prefix=PPC64
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66
; FIXME: we don't currently check for the operations themselves with CHECK-NEXT,
77
; because they are implemented in a very messy way with lwarx/stwcx.

‎llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.ll

Lines changed: 2 additions & 2 deletions
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@@ -1,9 +1,9 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu < %s |\
33
; RUN: FileCheck %s --check-prefix=CHECK-PWR8
4-
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
4+
; RUN: llc -verify-machineinstrs -mcpu=ppc -mtriple=powerpc64-unknown-linux-gnu \
55
; RUN: -mattr=-vsx < %s | FileCheck %s --check-prefix=CHECK-NOVSX
6-
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
6+
; RUN: llc -verify-machineinstrs -mcpu=ppc -mtriple=powerpc64-unknown-linux-gnu \
77
; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-PWR7
88
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix -mcpu=pwr7 \
99
; RUN: < %s | FileCheck %s --check-prefix=CHECK-PWR7

‎llvm/test/CodeGen/PowerPC/fma-assoc.ll

Lines changed: 2 additions & 2 deletions
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@@ -1,8 +1,8 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- -fp-contract=fast \
3-
; RUN: -mattr=-vsx -disable-ppc-vsx-fma-mutation=false | FileCheck %s
3+
; RUN: -mcpu=ppc -mattr=-vsx -disable-ppc-vsx-fma-mutation=false | FileCheck %s
44
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-ibm-aix-xcoff -fp-contract=fast \
5-
; RUN: -mattr=-vsx -disable-ppc-vsx-fma-mutation=false | FileCheck %s
5+
; RUN: -mcpu=ppc -mattr=-vsx -disable-ppc-vsx-fma-mutation=false | FileCheck %s
66
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu \
77
; RUN: -fp-contract=fast -mattr=+vsx -disable-ppc-vsx-fma-mutation=false \
88
; RUN: -mcpu=pwr7 | FileCheck -check-prefix=CHECK-VSX %s

‎llvm/test/CodeGen/PowerPC/fptoui-be-crash.ll

Lines changed: 1 addition & 1 deletion
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@@ -1,6 +1,6 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
22
; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names \
3-
; RUN: -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
3+
; RUN: -mcpu=ppc -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s
44
define dso_local void @calc_buffer() local_unnamed_addr #0 {
55
; CHECK-LABEL: calc_buffer:
66
; CHECK: # %bb.0:

‎llvm/test/CodeGen/PowerPC/frounds.ll

Lines changed: 1 addition & 1 deletion
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@@ -1,7 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -verify-machineinstrs < %s -mtriple=ppc32-- | FileCheck %s \
33
; RUN: -check-prefix=PPC32
4-
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64 | FileCheck %s \
4+
; RUN: llc -verify-machineinstrs < %s -mcpu=ppc -mtriple=powerpc64 | FileCheck %s \
55
; RUN: -check-prefix=PPC64
66
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le -mattr=-direct-move \
77
; RUN: | FileCheck %s -check-prefix=PPC64LE

‎llvm/test/CodeGen/PowerPC/ftrunc-legalize.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc -mtriple=powerpc64-- -mattr=altivec -verify-machineinstrs < %s | FileCheck %s
2+
; RUN: llc -mcpu=ppc -mtriple=powerpc64-- -mattr=altivec -verify-machineinstrs < %s | FileCheck %s
33

44
; This would assert because the widened vector op is
55
; legal/custom, but the scalar op is expanded.

‎llvm/test/CodeGen/PowerPC/hoist-logic.ll

Lines changed: 2 additions & 2 deletions
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11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc < %s -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s
3-
; RUN: llc < %s -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff | FileCheck %s
2+
; RUN: llc < %s -verify-machineinstrs -mcpu=ppc -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s
3+
; RUN: llc < %s -verify-machineinstrs -mcpu=ppc -mtriple=powerpc64-ibm-aix-xcoff | FileCheck %s
44

55
; This is good - eliminate an op by hoisting logic.
66

‎llvm/test/CodeGen/PowerPC/huge-frame-call.ll

Lines changed: 1 addition & 1 deletion
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@@ -1,7 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
22
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-linux-gnu < %s \
33
; RUN: 2>&1 | FileCheck --check-prefix=CHECK-LE %s
4-
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff < %s \
4+
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff -mcpu=ppc < %s \
55
; RUN: 2>&1 | FileCheck --check-prefix=CHECK-BE %s
66

77
%0 = type <{ i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, ptr, [8 x i8] }>

‎llvm/test/CodeGen/PowerPC/inc-of-add.ll

Lines changed: 3 additions & 3 deletions
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11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2-
; RUN: llc < %s -mtriple=ppc32-unknown-unknown | FileCheck %s --check-prefixes=ALL,PPC32
3-
; RUN: llc < %s -mtriple=powerpc64-unknown-unknown | FileCheck %s --check-prefixes=ALL,PPC64,PPC64BE
4-
; RUN: llc < %s -mtriple=powerpc64-ibm-aix-xcoff | FileCheck %s --check-prefixes=ALL,PPC64,PPC64BE,AIX-PPC64
2+
; RUN: llc < %s -mcpu=ppc -mtriple=ppc32-unknown-unknown | FileCheck %s --check-prefixes=ALL,PPC32
3+
; RUN: llc < %s -mcpu=ppc -mtriple=powerpc64-unknown-unknown | FileCheck %s --check-prefixes=ALL,PPC64,PPC64BE
4+
; RUN: llc < %s -mcpu=ppc -mtriple=powerpc64-ibm-aix-xcoff | FileCheck %s --check-prefixes=ALL,PPC64,PPC64BE,AIX-PPC64
55
; RUN: llc < %s -mtriple=powerpc64le-unknown-unknown | FileCheck %s --check-prefixes=ALL,PPC64,PPC64LE
66

77
; These two forms are equivalent:

‎llvm/test/CodeGen/PowerPC/kill_flag_verification.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
; RUN: llc < %s -mtriple powerpc64le-unknown-linux-gnu
2-
; RUN: llc < %s -mtriple powerpc64-unknown-linux-gnu
3-
; RUN: llc < %s -mtriple powerpc-ibm-aix
4-
; RUN: llc < %s -mtriple powerpc64-ibm-aix
2+
; RUN: llc < %s -mcpu=ppc -mtriple powerpc64-unknown-linux-gnu
3+
; RUN: llc < %s -mcpu=ppc -mtriple powerpc-ibm-aix
4+
; RUN: llc < %s -mcpu=ppc -mtriple powerpc64-ibm-aix
55

66
define void @xvcvdpsp_kill_flag() {
77
entry:

‎llvm/test/CodeGen/PowerPC/ldst-16-byte.mir

Lines changed: 1 addition & 1 deletion
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@@ -1,5 +1,5 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
# RUN: llc -simplify-mir -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff \
2+
# RUN: llc -simplify-mir -verify-machineinstrs -mcpu=ppc -mtriple=powerpc64-ibm-aix-xcoff \
33
# RUN: -stop-after=postrapseudos %s -o - | FileCheck %s
44

55
---

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