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[RISCV] Move ActiveElementsAffectResult to TSFlags. NFC (#101123)
As noted in https://github.com/llvm/llvm-project/pull/100367/files#r1695442138, RISCVMaskedPseudoInfo currently stores two things, whether or not a masked pseudo has an unmasked variant, and whether or not it's element-wise. These are separate things, so this patch splits the latter out into the underlying instruction's TSFlags to help make the semantics of #100367 more clear. To the best of my knowledge the only non-element-wise instructions in V are: - vredsum.vs and other reductions - vcompress.vm - vms*f.m - vcpop.m and vfirst.m - viota.m In vector crypto the instructions that operate on element groups are conservatively marked (this might be fine to relax later given since non-EGS multiple vls are reserved), as well as the SiFive extensions and XTHeadVdot.
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-24
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9 files changed

+42
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‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -123,6 +123,9 @@ enum {
123123
// 3 -> widening case
124124
TargetOverlapConstraintTypeShift = UsesVXRMShift + 1,
125125
TargetOverlapConstraintTypeMask = 3ULL << TargetOverlapConstraintTypeShift,
126+
127+
ActiveElementsAffectResultShift = TargetOverlapConstraintTypeShift + 2,
128+
ActiveElementsAffectResultMask = 1ULL << ActiveElementsAffectResultShift,
126129
};
127130

128131
// Helper functions to read TSFlags.
@@ -171,6 +174,12 @@ static inline bool hasRoundModeOp(uint64_t TSFlags) {
171174
/// \returns true if this instruction uses vxrm
172175
static inline bool usesVXRM(uint64_t TSFlags) { return TSFlags & UsesVXRMMask; }
173176

177+
/// \returns true if the result isn't element-wise,
178+
/// e.g. vredsum.vs/vcompress.vm/viota.m
179+
static inline bool activeElementsAffectResult(uint64_t TSFlags) {
180+
return TSFlags & ActiveElementsAffectResultMask;
181+
}
182+
174183
static inline unsigned getVLOpNum(const MCInstrDesc &Desc) {
175184
const uint64_t TSFlags = Desc.TSFlags;
176185
// This method is only called if we expect to have a VL operand, and all

‎llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@
1515
#include "MCTargetDesc/RISCVMCTargetDesc.h"
1616
#include "MCTargetDesc/RISCVMatInt.h"
1717
#include "RISCVISelLowering.h"
18+
#include "RISCVInstrInfo.h"
1819
#include "RISCVMachineFunctionInfo.h"
1920
#include "llvm/CodeGen/MachineFrameInfo.h"
2021
#include "llvm/IR/IntrinsicsRISCV.h"
@@ -3849,7 +3850,8 @@ bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N) {
38493850
// Some operations produce different elementwise results depending on the
38503851
// active elements, like viota.m or vredsum. This transformation is illegal
38513852
// for these if we change the active elements (i.e. mask or VL).
3852-
if (Info->ActiveElementsAffectResult) {
3853+
const MCInstrDesc &TrueBaseMCID = TII->get(RISCV::getRVVMCOpcode(TrueOpc));
3854+
if (RISCVII::activeElementsAffectResult(TrueBaseMCID.TSFlags)) {
38533855
if (Mask && !usesAllOnesMask(Mask, Glue))
38543856
return false;
38553857
if (TrueVL != VL)

‎llvm/lib/Target/RISCV/RISCVInstrFormats.td

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -223,6 +223,9 @@ class RVInstCommon<dag outs, dag ins, string opcodestr, string argstr,
223223
// 3 -> widening case
224224
bits<2> TargetOverlapConstraintType = 0;
225225
let TSFlags{22-21} = TargetOverlapConstraintType;
226+
227+
bit ActiveElementsAffectResult = 0;
228+
let TSFlags{23} = ActiveElementsAffectResult;
226229
}
227230

228231
class RVInst<dag outs, dag ins, string opcodestr, string argstr,

‎llvm/lib/Target/RISCV/RISCVInstrInfo.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -385,7 +385,6 @@ struct RISCVMaskedPseudoInfo {
385385
uint16_t MaskedPseudo;
386386
uint16_t UnmaskedPseudo;
387387
uint8_t MaskOpIdx;
388-
uint8_t ActiveElementsAffectResult : 1;
389388
};
390389
#define GET_RISCVMaskedPseudosTable_DECL
391390
#include "RISCVGenSearchableTables.inc"

‎llvm/lib/Target/RISCV/RISCVInstrInfoV.td

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1503,7 +1503,7 @@ defm VFNCVT_ROD_F_F_W : VNCVTF_FV_VS2<"vfncvt.rod.f.f.w", 0b010010, 0b10101>;
15031503
let Predicates = [HasVInstructions] in {
15041504

15051505
// Vector Single-Width Integer Reduction Instructions
1506-
let RVVConstraint = NoConstraint in {
1506+
let RVVConstraint = NoConstraint, ActiveElementsAffectResult = 1 in {
15071507
defm VREDSUM : VRED_MV_V<"vredsum", 0b000000>;
15081508
defm VREDMAXU : VREDMINMAX_MV_V<"vredmaxu", 0b000110>;
15091509
defm VREDMAX : VREDMINMAX_MV_V<"vredmax", 0b000111>;
@@ -1512,23 +1512,23 @@ defm VREDMIN : VREDMINMAX_MV_V<"vredmin", 0b000101>;
15121512
defm VREDAND : VRED_MV_V<"vredand", 0b000001>;
15131513
defm VREDOR : VRED_MV_V<"vredor", 0b000010>;
15141514
defm VREDXOR : VRED_MV_V<"vredxor", 0b000011>;
1515-
} // RVVConstraint = NoConstraint
1515+
} // RVVConstraint = NoConstraint, ActiveElementsAffectResult = 1
15161516

15171517
// Vector Widening Integer Reduction Instructions
1518-
let Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint in {
1518+
let Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint, ActiveElementsAffectResult = 1 in {
15191519
// Set earlyclobber for following instructions for second and mask operands.
15201520
// This has the downside that the earlyclobber constraint is too coarse and
15211521
// will impose unnecessary restrictions by not allowing the destination to
15221522
// overlap with the first (wide) operand.
15231523
defm VWREDSUMU : VWRED_IV_V<"vwredsumu", 0b110000>;
15241524
defm VWREDSUM : VWRED_IV_V<"vwredsum", 0b110001>;
1525-
} // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint
1525+
} // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint, ActiveElementsAffectResult = 1
15261526

15271527
} // Predicates = [HasVInstructions]
15281528

15291529
let Predicates = [HasVInstructionsAnyF] in {
15301530
// Vector Single-Width Floating-Point Reduction Instructions
1531-
let RVVConstraint = NoConstraint in {
1531+
let RVVConstraint = NoConstraint, ActiveElementsAffectResult = 1 in {
15321532
let Uses = [FRM], mayRaiseFPException = true in {
15331533
defm VFREDOSUM : VREDO_FV_V<"vfredosum", 0b000011>;
15341534
defm VFREDUSUM : VRED_FV_V<"vfredusum", 0b000001>;
@@ -1537,13 +1537,13 @@ let mayRaiseFPException = true in {
15371537
defm VFREDMAX : VREDMINMAX_FV_V<"vfredmax", 0b000111>;
15381538
defm VFREDMIN : VREDMINMAX_FV_V<"vfredmin", 0b000101>;
15391539
}
1540-
} // RVVConstraint = NoConstraint
1540+
} // RVVConstraint = NoConstraint, ActiveElementsAffectResult = 1
15411541

15421542
def : InstAlias<"vfredsum.vs $vd, $vs2, $vs1$vm",
15431543
(VFREDUSUM_VS VR:$vd, VR:$vs2, VR:$vs1, VMaskOp:$vm), 0>;
15441544

15451545
// Vector Widening Floating-Point Reduction Instructions
1546-
let Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint in {
1546+
let Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint, ActiveElementsAffectResult = 1 in {
15471547
// Set earlyclobber for following instructions for second and mask operands.
15481548
// This has the downside that the earlyclobber constraint is too coarse and
15491549
// will impose unnecessary restrictions by not allowing the destination to
@@ -1552,7 +1552,7 @@ let Uses = [FRM], mayRaiseFPException = true in {
15521552
defm VFWREDOSUM : VWREDO_FV_V<"vfwredosum", 0b110011>;
15531553
defm VFWREDUSUM : VWRED_FV_V<"vfwredusum", 0b110001>;
15541554
}
1555-
} // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint
1555+
} // Constraints = "@earlyclobber $vd", RVVConstraint = NoConstraint, ActiveElementsAffectResult = 1
15561556

15571557
def : InstAlias<"vfwredsum.vs $vd, $vs2, $vs1$vm",
15581558
(VFWREDUSUM_VS VR:$vd, VR:$vs2, VR:$vs1, VMaskOp:$vm), 0>;
@@ -1586,7 +1586,7 @@ def : InstAlias<"vmornot.mm $vd, $vs2, $vs1",
15861586
(VMORN_MM VR:$vd, VR:$vs2, VR:$vs1), 0>;
15871587

15881588
let hasSideEffects = 0, mayLoad = 0, mayStore = 0,
1589-
RVVConstraint = NoConstraint in {
1589+
RVVConstraint = NoConstraint, ActiveElementsAffectResult = 1 in {
15901590

15911591
// Vector mask population count vcpop
15921592
def VCPOP_M : RVInstV<0b010000, 0b10000, OPMVV, (outs GPR:$vd),
@@ -1600,12 +1600,12 @@ def VFIRST_M : RVInstV<0b010000, 0b10001, OPMVV, (outs GPR:$vd),
16001600
"vfirst.m", "$vd, $vs2$vm">,
16011601
SchedUnaryMC<"WriteVMFFSV", "ReadVMFFSV">;
16021602

1603-
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
1603+
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0, RVVConstraint = NoConstraint, ActiveElementsAffectResult = 1
16041604

16051605
def : InstAlias<"vpopc.m $vd, $vs2$vm",
16061606
(VCPOP_M GPR:$vd, VR:$vs2, VMaskOp:$vm), 0>;
16071607

1608-
let Constraints = "@earlyclobber $vd", RVVConstraint = Iota in {
1608+
let Constraints = "@earlyclobber $vd", RVVConstraint = Iota, ActiveElementsAffectResult = 1 in {
16091609

16101610
// vmsbf.m set-before-first mask bit
16111611
defm VMSBF_M : VMSFS_MV_V<"vmsbf.m", 0b010100, 0b00001>;
@@ -1616,7 +1616,7 @@ defm VMSOF_M : VMSFS_MV_V<"vmsof.m", 0b010100, 0b00010>;
16161616
// Vector Iota Instruction
16171617
defm VIOTA_M : VIOTA_MV_V<"viota.m", 0b010100, 0b10000>;
16181618

1619-
} // Constraints = "@earlyclobber $vd", RVVConstraint = Iota
1619+
} // Constraints = "@earlyclobber $vd", RVVConstraint = Iota, ActiveElementsAffectResult = 1
16201620

16211621
// Vector Element Index Instruction
16221622
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
@@ -1686,9 +1686,9 @@ def VRGATHEREI16_VV : VALUVV<0b001110, OPIVV, "vrgatherei16.vv">,
16861686
} // Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather
16871687

16881688
// Vector Compress Instruction
1689-
let Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress in {
1689+
let Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress, ActiveElementsAffectResult = 1 in {
16901690
defm VCOMPRESS_V : VCPR_MV_Mask<"vcompress", 0b010111>;
1691-
} // Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress
1691+
} // Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress, ActiveElementsAffectResult = 1
16921692

16931693
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isMoveReg = 1,
16941694
RVVConstraint = NoConstraint in {

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -561,17 +561,16 @@ def RISCVVIntrinsicsTable : GenericTable {
561561
// unmasked variant. For all but compares, both the masked and
562562
// unmasked variant have a passthru and policy operand. For compares,
563563
// neither has a policy op, and only the masked version has a passthru.
564-
class RISCVMaskedPseudo<bits<4> MaskIdx, bit ActiveAffectsRes=false> {
564+
class RISCVMaskedPseudo<bits<4> MaskIdx> {
565565
Pseudo MaskedPseudo = !cast<Pseudo>(NAME);
566566
Pseudo UnmaskedPseudo = !cast<Pseudo>(!subst("_MASK", "", NAME));
567567
bits<4> MaskOpIdx = MaskIdx;
568-
bit ActiveElementsAffectResult = ActiveAffectsRes;
569568
}
570569

571570
def RISCVMaskedPseudosTable : GenericTable {
572571
let FilterClass = "RISCVMaskedPseudo";
573572
let CppTypeName = "RISCVMaskedPseudoInfo";
574-
let Fields = ["MaskedPseudo", "UnmaskedPseudo", "MaskOpIdx", "ActiveElementsAffectResult"];
573+
let Fields = ["MaskedPseudo", "UnmaskedPseudo", "MaskOpIdx"];
575574
let PrimaryKey = ["MaskedPseudo"];
576575
let PrimaryKeyName = "getMaskedPseudoInfo";
577576
}
@@ -2065,7 +2064,7 @@ multiclass VPseudoVIOTA_M {
20652064
SchedUnary<"WriteVIotaV", "ReadVIotaV", mx,
20662065
forcePassthruRead=true>;
20672066
def "_" # mx # "_MASK" : VPseudoUnaryMask<m.vrclass, VR, constraint>,
2068-
RISCVMaskedPseudo<MaskIdx=2, ActiveAffectsRes=true>,
2067+
RISCVMaskedPseudo<MaskIdx=2>,
20692068
SchedUnary<"WriteVIotaV", "ReadVIotaV", mx,
20702069
forcePassthruRead=true>;
20712070
}
@@ -3162,7 +3161,7 @@ multiclass VPseudoTernaryWithTailPolicy<VReg RetClass,
31623161
defvar mx = MInfo.MX;
31633162
def "_" # mx # "_E" # sew : VPseudoTernaryNoMaskWithPolicy<RetClass, Op1Class, Op2Class>;
31643163
def "_" # mx # "_E" # sew # "_MASK" : VPseudoTernaryMaskPolicy<RetClass, Op1Class, Op2Class>,
3165-
RISCVMaskedPseudo<MaskIdx=3, ActiveAffectsRes=true>;
3164+
RISCVMaskedPseudo<MaskIdx=3>;
31663165
}
31673166
}
31683167

@@ -3179,7 +3178,7 @@ multiclass VPseudoTernaryWithTailPolicyRoundingMode<VReg RetClass,
31793178
def "_" # mx # "_E" # sew # "_MASK"
31803179
: VPseudoTernaryMaskPolicyRoundingMode<RetClass, Op1Class,
31813180
Op2Class>,
3182-
RISCVMaskedPseudo<MaskIdx=3, ActiveAffectsRes=true>;
3181+
RISCVMaskedPseudo<MaskIdx=3>;
31833182
}
31843183
}
31853184

‎llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -75,6 +75,7 @@ class RVInstVCCustom2<bits<4> funct6_hi4, bits<3> funct3, dag outs, dag ins,
7575

7676
let Uses = [VTYPE, VL];
7777
let RVVConstraint = NoConstraint;
78+
let ActiveElementsAffectResult = 1;
7879
}
7980

8081
class RVInstVCFCustom2<bits<4> funct6_hi4, bits<3> funct3, dag outs, dag ins,
@@ -98,6 +99,7 @@ class RVInstVCFCustom2<bits<4> funct6_hi4, bits<3> funct3, dag outs, dag ins,
9899

99100
let Uses = [VTYPE, VL];
100101
let RVVConstraint = NoConstraint;
102+
let ActiveElementsAffectResult = 1;
101103
}
102104

103105
class VCIXInfo<string suffix, VCIXType type, DAGOperand TyRd,

‎llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -235,13 +235,13 @@ class THStoreUpdate<bits<5> funct5, string opcodestr>
235235
//===----------------------------------------------------------------------===//
236236

237237
multiclass THVdotVMAQA_VX<string opcodestr, bits<6> funct6> {
238-
let RVVConstraint = WidenV in
238+
let RVVConstraint = WidenV, ActiveElementsAffectResult = 1 in
239239
def _VX : THVdotALUrVX<funct6, OPMVX, opcodestr # ".vx", EarlyClobber=1>;
240240
}
241241

242242
multiclass THVdotVMAQA<string opcodestr, bits<6> funct6>
243243
: THVdotVMAQA_VX<opcodestr, funct6> {
244-
let RVVConstraint = WidenV in
244+
let RVVConstraint = WidenV, ActiveElementsAffectResult = 1 in
245245
def _VV : THVdotALUrVV<funct6, OPMVX, opcodestr # ".vv", EarlyClobber=1>;
246246
}
247247

‎llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -140,6 +140,8 @@ let Predicates = [HasStdExtZvkb] in {
140140
defm VROR_V : VROR_IV_V_X_I<"vror", 0b010100>;
141141
} // Predicates = [HasStdExtZvkb]
142142

143+
let ActiveElementsAffectResult = 1 in {
144+
143145
let Predicates = [HasStdExtZvkg], RVVConstraint = NoConstraint in {
144146
def VGHSH_VV : PALUVVNoVmTernary<0b101100, OPMVV, "vghsh.vv">,
145147
SchedTernaryMC<"WriteVGHSHV", "ReadVGHSHV", "ReadVGHSHV",
@@ -188,6 +190,8 @@ let Predicates = [HasStdExtZvksh], RVVConstraint = VS2Constraint in {
188190
SchedUnaryMC<"WriteVSM3MEV", "ReadVSM3MEV">;
189191
} // Predicates = [HasStdExtZvksh]
190192

193+
} // ActiveElementsAffectResult = 1
194+
191195
//===----------------------------------------------------------------------===//
192196
// Pseudo instructions
193197
//===----------------------------------------------------------------------===//

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