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[RISCV] Use ForceTailAgnostic for masked vmsbf/vmsif/vmsof.m. (#94532)
These instructions use the mask policy, but always update the destination under tail agnostic policy.
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4 files changed

+25
-24
lines changed

4 files changed

+25
-24
lines changed

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2075,6 +2075,7 @@ multiclass VPseudoVSFS_M {
20752075
def "_M_" # mti.BX : VPseudoUnaryNoMaskNoPolicy<VR, VR, constraint>,
20762076
SchedUnary<"WriteVMSFSV", "ReadVMSFSV", mx,
20772077
forceMergeOpRead=true>;
2078+
let ForceTailAgnostic = true in
20782079
def "_M_" # mti.BX # "_MASK" : VPseudoUnaryMask<VR, VR, constraint>,
20792080
SchedUnary<"WriteVMSFSV", "ReadVMSFSV", mx,
20802081
forceMergeOpRead=true>;

‎llvm/test/CodeGen/RISCV/rvv/vmsbf.ll

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,7 @@ define <vscale x 1 x i1> @intrinsic_vmsbf_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1>
3333
; CHECK: # %bb.0: # %entry
3434
; CHECK-NEXT: vmv1r.v v10, v0
3535
; CHECK-NEXT: vmv1r.v v0, v9
36-
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
36+
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
3737
; CHECK-NEXT: vmsbf.m v10, v8, v0.t
3838
; CHECK-NEXT: vmv1r.v v0, v10
3939
; CHECK-NEXT: ret
@@ -75,7 +75,7 @@ define <vscale x 2 x i1> @intrinsic_vmsbf_mask_m_nxv2i1_nxv2i1(<vscale x 2 x i1>
7575
; CHECK: # %bb.0: # %entry
7676
; CHECK-NEXT: vmv1r.v v10, v0
7777
; CHECK-NEXT: vmv1r.v v0, v9
78-
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu
78+
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
7979
; CHECK-NEXT: vmsbf.m v10, v8, v0.t
8080
; CHECK-NEXT: vmv1r.v v0, v10
8181
; CHECK-NEXT: ret
@@ -117,7 +117,7 @@ define <vscale x 4 x i1> @intrinsic_vmsbf_mask_m_nxv4i1_nxv4i1(<vscale x 4 x i1>
117117
; CHECK: # %bb.0: # %entry
118118
; CHECK-NEXT: vmv1r.v v10, v0
119119
; CHECK-NEXT: vmv1r.v v0, v9
120-
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
120+
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
121121
; CHECK-NEXT: vmsbf.m v10, v8, v0.t
122122
; CHECK-NEXT: vmv1r.v v0, v10
123123
; CHECK-NEXT: ret
@@ -159,9 +159,9 @@ define <vscale x 8 x i1> @intrinsic_vmsbf_mask_m_nxv8i1_nxv8i1(<vscale x 8 x i1>
159159
; CHECK: # %bb.0: # %entry
160160
; CHECK-NEXT: vmv1r.v v10, v0
161161
; CHECK-NEXT: vmv1r.v v0, v9
162-
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
162+
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
163163
; CHECK-NEXT: vmsbf.m v10, v8, v0.t
164-
; CHECK-NEXT: vmv1r.v v0, v10
164+
; CHECK-NEXT: vmv.v.v v0, v10
165165
; CHECK-NEXT: ret
166166
entry:
167167
%a = call <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1(
@@ -201,7 +201,7 @@ define <vscale x 16 x i1> @intrinsic_vmsbf_mask_m_nxv16i1_nxv16i1(<vscale x 16 x
201201
; CHECK: # %bb.0: # %entry
202202
; CHECK-NEXT: vmv1r.v v10, v0
203203
; CHECK-NEXT: vmv1r.v v0, v9
204-
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu
204+
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
205205
; CHECK-NEXT: vmsbf.m v10, v8, v0.t
206206
; CHECK-NEXT: vmv1r.v v0, v10
207207
; CHECK-NEXT: ret
@@ -243,7 +243,7 @@ define <vscale x 32 x i1> @intrinsic_vmsbf_mask_m_nxv32i1_nxv32i1(<vscale x 32 x
243243
; CHECK: # %bb.0: # %entry
244244
; CHECK-NEXT: vmv1r.v v10, v0
245245
; CHECK-NEXT: vmv1r.v v0, v9
246-
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu
246+
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
247247
; CHECK-NEXT: vmsbf.m v10, v8, v0.t
248248
; CHECK-NEXT: vmv1r.v v0, v10
249249
; CHECK-NEXT: ret
@@ -285,7 +285,7 @@ define <vscale x 64 x i1> @intrinsic_vmsbf_mask_m_nxv64i1_nxv64i1(<vscale x 64 x
285285
; CHECK: # %bb.0: # %entry
286286
; CHECK-NEXT: vmv1r.v v10, v0
287287
; CHECK-NEXT: vmv1r.v v0, v9
288-
; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, mu
288+
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
289289
; CHECK-NEXT: vmsbf.m v10, v8, v0.t
290290
; CHECK-NEXT: vmv1r.v v0, v10
291291
; CHECK-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/vmsif.ll

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,7 @@ define <vscale x 1 x i1> @intrinsic_vmsif_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1>
3333
; CHECK: # %bb.0: # %entry
3434
; CHECK-NEXT: vmv1r.v v10, v0
3535
; CHECK-NEXT: vmv1r.v v0, v9
36-
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
36+
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
3737
; CHECK-NEXT: vmsif.m v10, v8, v0.t
3838
; CHECK-NEXT: vmv1r.v v0, v10
3939
; CHECK-NEXT: ret
@@ -75,7 +75,7 @@ define <vscale x 2 x i1> @intrinsic_vmsif_mask_m_nxv2i1_nxv2i1(<vscale x 2 x i1>
7575
; CHECK: # %bb.0: # %entry
7676
; CHECK-NEXT: vmv1r.v v10, v0
7777
; CHECK-NEXT: vmv1r.v v0, v9
78-
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu
78+
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
7979
; CHECK-NEXT: vmsif.m v10, v8, v0.t
8080
; CHECK-NEXT: vmv1r.v v0, v10
8181
; CHECK-NEXT: ret
@@ -117,7 +117,7 @@ define <vscale x 4 x i1> @intrinsic_vmsif_mask_m_nxv4i1_nxv4i1(<vscale x 4 x i1>
117117
; CHECK: # %bb.0: # %entry
118118
; CHECK-NEXT: vmv1r.v v10, v0
119119
; CHECK-NEXT: vmv1r.v v0, v9
120-
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
120+
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
121121
; CHECK-NEXT: vmsif.m v10, v8, v0.t
122122
; CHECK-NEXT: vmv1r.v v0, v10
123123
; CHECK-NEXT: ret
@@ -159,9 +159,9 @@ define <vscale x 8 x i1> @intrinsic_vmsif_mask_m_nxv8i1_nxv8i1(<vscale x 8 x i1>
159159
; CHECK: # %bb.0: # %entry
160160
; CHECK-NEXT: vmv1r.v v10, v0
161161
; CHECK-NEXT: vmv1r.v v0, v9
162-
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
162+
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
163163
; CHECK-NEXT: vmsif.m v10, v8, v0.t
164-
; CHECK-NEXT: vmv1r.v v0, v10
164+
; CHECK-NEXT: vmv.v.v v0, v10
165165
; CHECK-NEXT: ret
166166
entry:
167167
%a = call <vscale x 8 x i1> @llvm.riscv.vmsif.mask.nxv8i1(
@@ -201,7 +201,7 @@ define <vscale x 16 x i1> @intrinsic_vmsif_mask_m_nxv16i1_nxv16i1(<vscale x 16 x
201201
; CHECK: # %bb.0: # %entry
202202
; CHECK-NEXT: vmv1r.v v10, v0
203203
; CHECK-NEXT: vmv1r.v v0, v9
204-
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu
204+
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
205205
; CHECK-NEXT: vmsif.m v10, v8, v0.t
206206
; CHECK-NEXT: vmv1r.v v0, v10
207207
; CHECK-NEXT: ret
@@ -243,7 +243,7 @@ define <vscale x 32 x i1> @intrinsic_vmsif_mask_m_nxv32i1_nxv32i1(<vscale x 32 x
243243
; CHECK: # %bb.0: # %entry
244244
; CHECK-NEXT: vmv1r.v v10, v0
245245
; CHECK-NEXT: vmv1r.v v0, v9
246-
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu
246+
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
247247
; CHECK-NEXT: vmsif.m v10, v8, v0.t
248248
; CHECK-NEXT: vmv1r.v v0, v10
249249
; CHECK-NEXT: ret
@@ -285,7 +285,7 @@ define <vscale x 64 x i1> @intrinsic_vmsif_mask_m_nxv64i1_nxv64i1(<vscale x 64 x
285285
; CHECK: # %bb.0: # %entry
286286
; CHECK-NEXT: vmv1r.v v10, v0
287287
; CHECK-NEXT: vmv1r.v v0, v9
288-
; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, mu
288+
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
289289
; CHECK-NEXT: vmsif.m v10, v8, v0.t
290290
; CHECK-NEXT: vmv1r.v v0, v10
291291
; CHECK-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/vmsof.ll

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -33,7 +33,7 @@ define <vscale x 1 x i1> @intrinsic_vmsof_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1>
3333
; CHECK: # %bb.0: # %entry
3434
; CHECK-NEXT: vmv1r.v v10, v0
3535
; CHECK-NEXT: vmv1r.v v0, v9
36-
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu
36+
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
3737
; CHECK-NEXT: vmsof.m v10, v8, v0.t
3838
; CHECK-NEXT: vmv1r.v v0, v10
3939
; CHECK-NEXT: ret
@@ -75,7 +75,7 @@ define <vscale x 2 x i1> @intrinsic_vmsof_mask_m_nxv2i1_nxv2i1(<vscale x 2 x i1>
7575
; CHECK: # %bb.0: # %entry
7676
; CHECK-NEXT: vmv1r.v v10, v0
7777
; CHECK-NEXT: vmv1r.v v0, v9
78-
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, tu, mu
78+
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
7979
; CHECK-NEXT: vmsof.m v10, v8, v0.t
8080
; CHECK-NEXT: vmv1r.v v0, v10
8181
; CHECK-NEXT: ret
@@ -117,7 +117,7 @@ define <vscale x 4 x i1> @intrinsic_vmsof_mask_m_nxv4i1_nxv4i1(<vscale x 4 x i1>
117117
; CHECK: # %bb.0: # %entry
118118
; CHECK-NEXT: vmv1r.v v10, v0
119119
; CHECK-NEXT: vmv1r.v v0, v9
120-
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, mu
120+
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
121121
; CHECK-NEXT: vmsof.m v10, v8, v0.t
122122
; CHECK-NEXT: vmv1r.v v0, v10
123123
; CHECK-NEXT: ret
@@ -159,9 +159,9 @@ define <vscale x 8 x i1> @intrinsic_vmsof_mask_m_nxv8i1_nxv8i1(<vscale x 8 x i1>
159159
; CHECK: # %bb.0: # %entry
160160
; CHECK-NEXT: vmv1r.v v10, v0
161161
; CHECK-NEXT: vmv1r.v v0, v9
162-
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, mu
162+
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
163163
; CHECK-NEXT: vmsof.m v10, v8, v0.t
164-
; CHECK-NEXT: vmv1r.v v0, v10
164+
; CHECK-NEXT: vmv.v.v v0, v10
165165
; CHECK-NEXT: ret
166166
entry:
167167
%a = call <vscale x 8 x i1> @llvm.riscv.vmsof.mask.nxv8i1(
@@ -201,7 +201,7 @@ define <vscale x 16 x i1> @intrinsic_vmsof_mask_m_nxv16i1_nxv16i1(<vscale x 16 x
201201
; CHECK: # %bb.0: # %entry
202202
; CHECK-NEXT: vmv1r.v v10, v0
203203
; CHECK-NEXT: vmv1r.v v0, v9
204-
; CHECK-NEXT: vsetvli zero, a0, e8, m2, tu, mu
204+
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
205205
; CHECK-NEXT: vmsof.m v10, v8, v0.t
206206
; CHECK-NEXT: vmv1r.v v0, v10
207207
; CHECK-NEXT: ret
@@ -243,7 +243,7 @@ define <vscale x 32 x i1> @intrinsic_vmsof_mask_m_nxv32i1_nxv32i1(<vscale x 32 x
243243
; CHECK: # %bb.0: # %entry
244244
; CHECK-NEXT: vmv1r.v v10, v0
245245
; CHECK-NEXT: vmv1r.v v0, v9
246-
; CHECK-NEXT: vsetvli zero, a0, e8, m4, tu, mu
246+
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
247247
; CHECK-NEXT: vmsof.m v10, v8, v0.t
248248
; CHECK-NEXT: vmv1r.v v0, v10
249249
; CHECK-NEXT: ret
@@ -285,7 +285,7 @@ define <vscale x 64 x i1> @intrinsic_vmsof_mask_m_nxv64i1_nxv64i1(<vscale x 64 x
285285
; CHECK: # %bb.0: # %entry
286286
; CHECK-NEXT: vmv1r.v v10, v0
287287
; CHECK-NEXT: vmv1r.v v0, v9
288-
; CHECK-NEXT: vsetvli zero, a0, e8, m8, tu, mu
288+
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
289289
; CHECK-NEXT: vmsof.m v10, v8, v0.t
290290
; CHECK-NEXT: vmv1r.v v0, v10
291291
; CHECK-NEXT: ret

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