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[flang] fix ppc test broken after #74709 (#74826)
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‎flang/test/Lower/PowerPC/ppc-vec-store.f90

Lines changed: 48 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -89,10 +89,10 @@ subroutine vec_st_vi4i4via4(arg1, arg2, arg3, i)
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! LLVMIR: %[[i:.*]] = load i32, ptr %3, align 4
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! LLVMIR: %[[iext:.*]] = sext i32 %[[i]] to i64
92-
! LLVMIR: %[[iextsub:.*]] = sub i64 %[[iext]], 1
93-
! LLVMIR: %[[iextmul:.*]] = mul i64 %[[iextsub]], 1
94-
! LLVMIR: %[[iextmul2:.*]] = mul i64 %[[iextmul]], 1
95-
! LLVMIR: %[[iextadd:.*]] = add i64 %[[iextmul2]], 0
92+
! LLVMIR: %[[iextsub:.*]] = sub nsw i64 %[[iext]], 1
93+
! LLVMIR: %[[iextmul:.*]] = mul nsw i64 %[[iextsub]], 1
94+
! LLVMIR: %[[iextmul2:.*]] = mul nsw i64 %[[iextmul]], 1
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! LLVMIR: %[[iextadd:.*]] = add nsw i64 %[[iextmul2]], 0
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! LLVMIR: %[[gep1:.*]] = getelementptr <4 x i32>, ptr %2, i64 %[[iextadd]]
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! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %0, align 16
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! LLVMIR: %[[arg2:.*]] = load i32, ptr %1, align 4
@@ -206,10 +206,10 @@ subroutine vec_ste_vi4i4ia4(arg1, arg2, arg3, i)
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! LLVMIR: %[[i:.*]] = load i32, ptr %3, align 4
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! LLVMIR: %[[iext:.*]] = sext i32 %[[i]] to i64
209-
! LLVMIR: %[[isub:.*]] = sub i64 %[[iext]], 1
210-
! LLVMIR: %[[imul1:.*]] = mul i64 %[[isub]], 1
211-
! LLVMIR: %[[imul2:.*]] = mul i64 %[[imul1]], 1
212-
! LLVMIR: %[[iadd:.*]] = add i64 %[[imul2]], 0
209+
! LLVMIR: %[[isub:.*]] = sub nsw i64 %[[iext]], 1
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! LLVMIR: %[[imul1:.*]] = mul nsw i64 %[[isub]], 1
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! LLVMIR: %[[imul2:.*]] = mul nsw i64 %[[imul1]], 1
212+
! LLVMIR: %[[iadd:.*]] = add nsw i64 %[[imul2]], 0
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! LLVMIR: %[[gep1:.*]] = getelementptr i32, ptr %2, i64 %[[iadd]]
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! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %0, align 16
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! LLVMIR: %[[arg2:.*]] = load i32, ptr %1, align 4
@@ -244,10 +244,10 @@ subroutine vec_stxv_test_vi4i8ia4(arg1, arg2, arg3, i)
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! LLVMIR: %[[i:.*]] = load i32, ptr %3, align 4
246246
! LLVMIR: %[[iext:.*]] = sext i32 %[[i]] to i64
247-
! LLVMIR: %[[isub:.*]] = sub i64 %[[iext]], 1
248-
! LLVMIR: %[[imul1:.*]] = mul i64 %[[isub]], 1
249-
! LLVMIR: %[[imul2:.*]] = mul i64 %[[imul1]], 1
250-
! LLVMIR: %[[iadd:.*]] = add i64 %[[imul2]], 0
247+
! LLVMIR: %[[isub:.*]] = sub nsw i64 %[[iext]], 1
248+
! LLVMIR: %[[imul1:.*]] = mul nsw i64 %[[isub]], 1
249+
! LLVMIR: %[[imul2:.*]] = mul nsw i64 %[[imul1]], 1
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! LLVMIR: %[[iadd:.*]] = add nsw i64 %[[imul2]], 0
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! LLVMIR: %[[gep1:.*]] = getelementptr i32, ptr %2, i64 %[[iadd]]
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! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %0, align 16
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! LLVMIR: %[[arg2:.*]] = load i64, ptr %1, align 8
@@ -278,10 +278,10 @@ subroutine vec_stxv_test_vi4i4vai4(arg1, arg2, arg3, i)
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! LLVMIR: %[[i:.*]] = load i32, ptr %3, align 4
280280
! LLVMIR: %[[iext:.*]] = sext i32 %[[i]] to i64
281-
! LLVMIR: %[[isub:.*]] = sub i64 %[[iext]], 1
282-
! LLVMIR: %[[imul1:.*]] = mul i64 %[[isub]], 1
283-
! LLVMIR: %[[imul2:.*]] = mul i64 %[[imul1]], 1
284-
! LLVMIR: %[[iadd:.*]] = add i64 %[[imul2]], 0
281+
! LLVMIR: %[[isub:.*]] = sub nsw i64 %[[iext]], 1
282+
! LLVMIR: %[[imul1:.*]] = mul nsw i64 %[[isub]], 1
283+
! LLVMIR: %[[imul2:.*]] = mul nsw i64 %[[imul1]], 1
284+
! LLVMIR: %[[iadd:.*]] = add nsw i64 %[[imul2]], 0
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! LLVMIR: %[[gep1:.*]] = getelementptr <4 x i32>, ptr %2, i64 %[[iadd]]
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! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %0, align 16
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! LLVMIR: %[[arg2:.*]] = load i32, ptr %1, align 4
@@ -317,10 +317,10 @@ subroutine vec_xst_test_vi4i8ia4(arg1, arg2, arg3, i)
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! LLVMIR: %[[i:.*]] = load i32, ptr %3, align 4
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! LLVMIR: %[[iext:.*]] = sext i32 %[[i]] to i64
320-
! LLVMIR: %[[isub:.*]] = sub i64 %[[iext]], 1
321-
! LLVMIR: %[[imul1:.*]] = mul i64 %[[isub]], 1
322-
! LLVMIR: %[[imul2:.*]] = mul i64 %[[imul1]], 1
323-
! LLVMIR: %[[iadd:.*]] = add i64 %[[imul2]], 0
320+
! LLVMIR: %[[isub:.*]] = sub nsw i64 %[[iext]], 1
321+
! LLVMIR: %[[imul1:.*]] = mul nsw i64 %[[isub]], 1
322+
! LLVMIR: %[[imul2:.*]] = mul nsw i64 %[[imul1]], 1
323+
! LLVMIR: %[[iadd:.*]] = add nsw i64 %[[imul2]], 0
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! LLVMIR: %[[gep1:.*]] = getelementptr i32, ptr %2, i64 %[[iadd]]
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! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %0, align 16
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! LLVMIR: %[[arg2:.*]] = load i64, ptr %1, align 8
@@ -351,10 +351,10 @@ subroutine vec_xst_test_vi4i4vai4(arg1, arg2, arg3, i)
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! LLVMIR: %[[i:.*]] = load i32, ptr %3, align 4
353353
! LLVMIR: %[[iext:.*]] = sext i32 %[[i]] to i64
354-
! LLVMIR: %[[isub:.*]] = sub i64 %[[iext]], 1
355-
! LLVMIR: %[[imul1:.*]] = mul i64 %[[isub]], 1
356-
! LLVMIR: %[[imul2:.*]] = mul i64 %[[imul1]], 1
357-
! LLVMIR: %[[iadd:.*]] = add i64 %[[imul2]], 0
354+
! LLVMIR: %[[isub:.*]] = sub nsw i64 %[[iext]], 1
355+
! LLVMIR: %[[imul1:.*]] = mul nsw i64 %[[isub]], 1
356+
! LLVMIR: %[[imul2:.*]] = mul nsw i64 %[[imul1]], 1
357+
! LLVMIR: %[[iadd:.*]] = add nsw i64 %[[imul2]], 0
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! LLVMIR: %[[gep1:.*]] = getelementptr <4 x i32>, ptr %2, i64 %[[iadd]]
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! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %0, align 16
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! LLVMIR: %[[arg2:.*]] = load i32, ptr %1, align 4
@@ -390,10 +390,10 @@ subroutine vec_xst_be_test_vi4i8ia4(arg1, arg2, arg3, i)
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! LLVMIR: %[[i:.*]] = load i32, ptr %3, align 4
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! LLVMIR: %[[iext:.*]] = sext i32 %[[i]] to i64
393-
! LLVMIR: %[[isub:.*]] = sub i64 %[[iext]], 1
394-
! LLVMIR: %[[imul1:.*]] = mul i64 %[[isub]], 1
395-
! LLVMIR: %[[imul2:.*]] = mul i64 %[[imul1]], 1
396-
! LLVMIR: %[[iadd:.*]] = add i64 %[[imul2]], 0
393+
! LLVMIR: %[[isub:.*]] = sub nsw i64 %[[iext]], 1
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! LLVMIR: %[[imul1:.*]] = mul nsw i64 %[[isub]], 1
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! LLVMIR: %[[imul2:.*]] = mul nsw i64 %[[imul1]], 1
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! LLVMIR: %[[iadd:.*]] = add nsw i64 %[[imul2]], 0
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! LLVMIR: %[[gep1:.*]] = getelementptr i32, ptr %2, i64 %[[iadd]]
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! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %0, align 16
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! LLVMIR: %[[arg2:.*]] = load i64, ptr %1, align 8
@@ -426,10 +426,10 @@ subroutine vec_xst_be_test_vi4i4vai4(arg1, arg2, arg3, i)
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! LLVMIR: %[[i:.*]] = load i32, ptr %3, align 4
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! LLVMIR: %[[iext:.*]] = sext i32 %[[i]] to i64
429-
! LLVMIR: %[[isub:.*]] = sub i64 %[[iext]], 1
430-
! LLVMIR: %[[imul1:.*]] = mul i64 %[[isub]], 1
431-
! LLVMIR: %[[imul2:.*]] = mul i64 %[[imul1]], 1
432-
! LLVMIR: %[[iadd:.*]] = add i64 %[[imul2]], 0
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! LLVMIR: %[[isub:.*]] = sub nsw i64 %[[iext]], 1
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! LLVMIR: %[[imul1:.*]] = mul nsw i64 %[[isub]], 1
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! LLVMIR: %[[imul2:.*]] = mul nsw i64 %[[imul1]], 1
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! LLVMIR: %[[iadd:.*]] = add nsw i64 %[[imul2]], 0
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! LLVMIR: %[[gep1:.*]] = getelementptr <4 x i32>, ptr %2, i64 %[[iadd]]
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! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %0, align 16
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! LLVMIR: %[[arg2:.*]] = load i32, ptr %1, align 4
@@ -467,10 +467,10 @@ subroutine vec_xstd2_test_vi4i8ia4(arg1, arg2, arg3, i)
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! LLVMIR: %[[i:.*]] = load i32, ptr %3, align 4
469469
! LLVMIR: %[[iext:.*]] = sext i32 %[[i]] to i64
470-
! LLVMIR: %[[isub:.*]] = sub i64 %[[iext]], 1
471-
! LLVMIR: %[[imul1:.*]] = mul i64 %[[isub]], 1
472-
! LLVMIR: %[[imul2:.*]] = mul i64 %[[imul1]], 1
473-
! LLVMIR: %[[iadd:.*]] = add i64 %[[imul2]], 0
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! LLVMIR: %[[isub:.*]] = sub nsw i64 %[[iext]], 1
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! LLVMIR: %[[imul1:.*]] = mul nsw i64 %[[isub]], 1
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! LLVMIR: %[[imul2:.*]] = mul nsw i64 %[[imul1]], 1
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! LLVMIR: %[[iadd:.*]] = add nsw i64 %[[imul2]], 0
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! LLVMIR: %[[gep1:.*]] = getelementptr i32, ptr %2, i64 %[[iadd]]
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! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %0, align 16
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! LLVMIR: %[[arg2:.*]] = load i64, ptr %1, align 8
@@ -503,10 +503,10 @@ subroutine vec_xstd2_test_vi4i4vai4(arg1, arg2, arg3, i)
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! LLVMIR: %[[i:.*]] = load i32, ptr %3, align 4
505505
! LLVMIR: %[[iext:.*]] = sext i32 %[[i]] to i64
506-
! LLVMIR: %[[isub:.*]] = sub i64 %[[iext]], 1
507-
! LLVMIR: %[[imul1:.*]] = mul i64 %[[isub]], 1
508-
! LLVMIR: %[[imul2:.*]] = mul i64 %[[imul1]], 1
509-
! LLVMIR: %[[iadd:.*]] = add i64 %[[imul2]], 0
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! LLVMIR: %[[isub:.*]] = sub nsw i64 %[[iext]], 1
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! LLVMIR: %[[imul1:.*]] = mul nsw i64 %[[isub]], 1
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! LLVMIR: %[[imul2:.*]] = mul nsw i64 %[[imul1]], 1
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! LLVMIR: %[[iadd:.*]] = add nsw i64 %[[imul2]], 0
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! LLVMIR: %[[gep1:.*]] = getelementptr <4 x i32>, ptr %2, i64 %[[iadd]]
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! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %0, align 16
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! LLVMIR: %[[arg2:.*]] = load i32, ptr %1, align 4
@@ -543,10 +543,10 @@ subroutine vec_xstw4_test_vi4i8ia4(arg1, arg2, arg3, i)
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! LLVMIR: %[[i:.*]] = load i32, ptr %3, align 4
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! LLVMIR: %[[iext:.*]] = sext i32 %[[i]] to i64
546-
! LLVMIR: %[[isub:.*]] = sub i64 %[[iext]], 1
547-
! LLVMIR: %[[imul1:.*]] = mul i64 %[[isub]], 1
548-
! LLVMIR: %[[imul2:.*]] = mul i64 %[[imul1]], 1
549-
! LLVMIR: %[[iadd:.*]] = add i64 %[[imul2]], 0
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! LLVMIR: %[[isub:.*]] = sub nsw i64 %[[iext]], 1
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! LLVMIR: %[[imul1:.*]] = mul nsw i64 %[[isub]], 1
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! LLVMIR: %[[imul2:.*]] = mul nsw i64 %[[imul1]], 1
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! LLVMIR: %[[iadd:.*]] = add nsw i64 %[[imul2]], 0
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! LLVMIR: %[[gep1:.*]] = getelementptr i32, ptr %2, i64 %[[iadd]]
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! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %0, align 16
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! LLVMIR: %[[arg2:.*]] = load i64, ptr %1, align 8
@@ -578,10 +578,10 @@ subroutine vec_xstw4_test_vi4i4vai4(arg1, arg2, arg3, i)
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! LLVMIR: %[[i:.*]] = load i32, ptr %3, align 4
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! LLVMIR: %[[iext:.*]] = sext i32 %[[i]] to i64
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! LLVMIR: %[[isub:.*]] = sub i64 %[[iext]], 1
582-
! LLVMIR: %[[imul1:.*]] = mul i64 %[[isub]], 1
583-
! LLVMIR: %[[imul2:.*]] = mul i64 %[[imul1]], 1
584-
! LLVMIR: %[[iadd:.*]] = add i64 %[[imul2]], 0
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! LLVMIR: %[[isub:.*]] = sub nsw i64 %[[iext]], 1
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! LLVMIR: %[[imul1:.*]] = mul nsw i64 %[[isub]], 1
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! LLVMIR: %[[imul2:.*]] = mul nsw i64 %[[imul1]], 1
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! LLVMIR: %[[iadd:.*]] = add nsw i64 %[[imul2]], 0
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! LLVMIR: %[[gep1:.*]] = getelementptr <4 x i32>, ptr %2, i64 %[[iadd]]
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! LLVMIR: %[[arg1:.*]] = load <4 x i32>, ptr %0, align 16
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! LLVMIR: %[[arg2:.*]] = load i32, ptr %1, align 4

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