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Revert "[PowerPC] Deprecate uses of ISD::ADDC/ISD::ADDE/ISD::SUBC/ISD::SUBE (#116984)"
This reverts commit 7763119 (leaving the modifications from 03cb46d)..
1 parent 760ec2c commit aa9e519

29 files changed

+411
-600
lines changed

‎llvm/lib/Target/PowerPC/PPCISelLowering.cpp

Lines changed: 55 additions & 131 deletions
Original file line numberDiff line numberDiff line change
@@ -197,11 +197,6 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
197197
}
198198

199199
setOperationAction(ISD::UADDO, RegVT, Custom);
200-
setOperationAction(ISD::USUBO, RegVT, Custom);
201-
202-
// PowerPC uses addo_carry,subo_carry to propagate carry.
203-
setOperationAction(ISD::UADDO_CARRY, RegVT, Custom);
204-
setOperationAction(ISD::USUBO_CARRY, RegVT, Custom);
205200

206201
// On P10, the default lowering generates better code using the
207202
// setbc instruction.
@@ -265,6 +260,15 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
265260
setIndexedStoreAction(ISD::PRE_INC, MVT::f64, Legal);
266261
}
267262

263+
// PowerPC uses ADDC/ADDE/SUBC/SUBE to propagate carry.
264+
const MVT ScalarIntVTs[] = { MVT::i32, MVT::i64 };
265+
for (MVT VT : ScalarIntVTs) {
266+
setOperationAction(ISD::ADDC, VT, Legal);
267+
setOperationAction(ISD::ADDE, VT, Legal);
268+
setOperationAction(ISD::SUBC, VT, Legal);
269+
setOperationAction(ISD::SUBE, VT, Legal);
270+
}
271+
268272
if (Subtarget.useCRBits()) {
269273
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
270274

@@ -1850,14 +1854,6 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
18501854
return "PPCISD::SETBC";
18511855
case PPCISD::SETBCR:
18521856
return "PPCISD::SETBCR";
1853-
case PPCISD::ADDC:
1854-
return "PPCISD::ADDC";
1855-
case PPCISD::ADDE:
1856-
return "PPCISD::ADDE";
1857-
case PPCISD::SUBC:
1858-
return "PPCISD::SUBC";
1859-
case PPCISD::SUBE:
1860-
return "PPCISD::SUBE";
18611857
}
18621858
return nullptr;
18631859
}
@@ -12017,74 +12013,43 @@ SDValue PPCTargetLowering::LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const {
1201712013
llvm_unreachable("ERROR:Should return for all cases within swtich.");
1201812014
}
1201912015

12020-
static SDValue ConvertCarryValueToCarryFlag(EVT SumType, SDValue Value,
12021-
SelectionDAG &DAG,
12022-
const PPCSubtarget &STI) {
12023-
SDLoc DL(Value);
12024-
if (STI.useCRBits())
12025-
Value = DAG.getNode(ISD::SELECT, DL, SumType, Value,
12026-
DAG.getConstant(1, DL, SumType),
12027-
DAG.getConstant(0, DL, SumType));
12028-
else
12029-
Value = DAG.getZExtOrTrunc(Value, DL, SumType);
12030-
SDValue Sum = DAG.getNode(PPCISD::ADDC, DL, DAG.getVTList(SumType, MVT::i32),
12031-
Value, DAG.getAllOnesConstant(DL, SumType));
12032-
return Sum.getValue(1);
12033-
}
12016+
SDValue PPCTargetLowering::LowerUaddo(SDValue Op, SelectionDAG &DAG) const {
12017+
// Default to target independent lowering if there is a logical user of the
12018+
// carry-bit.
12019+
for (SDNode *U : Op->users()) {
12020+
if (U->getOpcode() == ISD::SELECT)
12021+
return SDValue();
12022+
if (ISD::isBitwiseLogicOp(U->getOpcode())) {
12023+
for (unsigned i = 0, ie = U->getNumOperands(); i != ie; ++i) {
12024+
if (U->getOperand(i).getOpcode() != ISD::UADDO &&
12025+
U->getOperand(i).getOpcode() != ISD::MERGE_VALUES)
12026+
return SDValue();
12027+
}
12028+
}
12029+
}
12030+
SDValue LHS = Op.getOperand(0);
12031+
SDValue RHS = Op.getOperand(1);
12032+
SDLoc dl(Op);
1203412033

12035-
static SDValue ConvertCarryFlagToCarryValue(EVT SumType, SDValue Flag,
12036-
EVT CarryType, SelectionDAG &DAG,
12037-
const PPCSubtarget &STI) {
12038-
SDLoc DL(Flag);
12039-
SDValue Zero = DAG.getConstant(0, DL, SumType);
12040-
SDValue Carry = DAG.getNode(
12041-
PPCISD::ADDE, DL, DAG.getVTList(SumType, MVT::i32), Zero, Zero, Flag);
12042-
if (STI.useCRBits())
12043-
return DAG.getSetCC(DL, CarryType, Carry, Zero, ISD::SETNE);
12044-
return DAG.getZExtOrTrunc(Carry, DL, CarryType);
12045-
}
12034+
// Default to target independent lowering for special cases handled there.
12035+
if (isOneConstant(RHS) || isAllOnesConstant(RHS))
12036+
return SDValue();
1204612037

12047-
SDValue PPCTargetLowering::LowerADDSUBO(SDValue Op, SelectionDAG &DAG) const {
12038+
EVT VT = Op.getNode()->getValueType(0);
1204812039

12049-
SDLoc DL(Op);
12050-
SDNode *N = Op.getNode();
12051-
EVT VT = N->getValueType(0);
12052-
EVT CarryType = N->getValueType(1);
12053-
unsigned Opc = N->getOpcode();
12054-
bool IsAdd = Opc == ISD::UADDO;
12055-
Opc = IsAdd ? PPCISD::ADDC : PPCISD::SUBC;
12056-
SDValue Sum = DAG.getNode(Opc, DL, DAG.getVTList(VT, MVT::i32),
12057-
N->getOperand(0), N->getOperand(1));
12058-
SDValue Carry = ConvertCarryFlagToCarryValue(VT, Sum.getValue(1), CarryType,
12059-
DAG, Subtarget);
12060-
if (!IsAdd)
12061-
Carry = DAG.getNode(ISD::XOR, DL, CarryType, Carry,
12062-
DAG.getAllOnesConstant(DL, CarryType));
12063-
return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, Carry);
12064-
}
12065-
12066-
SDValue PPCTargetLowering::LowerADDSUBO_CARRY(SDValue Op,
12067-
SelectionDAG &DAG) const {
12068-
SDLoc DL(Op);
12069-
SDNode *N = Op.getNode();
12070-
unsigned Opc = N->getOpcode();
12071-
EVT VT = N->getValueType(0);
12072-
EVT CarryType = N->getValueType(1);
12073-
SDValue CarryOp = N->getOperand(2);
12074-
bool IsAdd = Opc == ISD::UADDO_CARRY;
12075-
Opc = IsAdd ? PPCISD::ADDE : PPCISD::SUBE;
12076-
if (!IsAdd)
12077-
CarryOp = DAG.getNode(ISD::XOR, DL, CarryOp.getValueType(), CarryOp,
12078-
DAG.getAllOnesConstant(DL, CarryOp.getValueType()));
12079-
CarryOp = ConvertCarryValueToCarryFlag(VT, CarryOp, DAG, Subtarget);
12080-
SDValue Sum = DAG.getNode(Opc, DL, DAG.getVTList(VT, MVT::i32),
12081-
Op.getOperand(0), Op.getOperand(1), CarryOp);
12082-
CarryOp = ConvertCarryFlagToCarryValue(VT, Sum.getValue(1), CarryType, DAG,
12083-
Subtarget);
12084-
if (!IsAdd)
12085-
CarryOp = DAG.getNode(ISD::XOR, DL, CarryOp.getValueType(), CarryOp,
12086-
DAG.getAllOnesConstant(DL, CarryOp.getValueType()));
12087-
return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, CarryOp);
12040+
SDValue ADDC;
12041+
SDValue Overflow;
12042+
SDVTList VTs = Op.getNode()->getVTList();
12043+
12044+
ADDC = DAG.getNode(ISD::ADDC, dl, DAG.getVTList(VT, MVT::Glue), LHS, RHS);
12045+
Overflow = DAG.getNode(ISD::ADDE, dl, DAG.getVTList(VT, MVT::Glue),
12046+
DAG.getConstant(0, dl, VT), DAG.getConstant(0, dl, VT),
12047+
ADDC.getValue(1));
12048+
SDValue OverflowTrunc =
12049+
DAG.getNode(ISD::TRUNCATE, dl, Op.getNode()->getValueType(1), Overflow);
12050+
SDValue Res =
12051+
DAG.getNode(ISD::MERGE_VALUES, dl, VTs, ADDC.getValue(0), OverflowTrunc);
12052+
return Res;
1208812053
}
1208912054

1209012055
SDValue PPCTargetLowering::LowerSSUBO(SDValue Op, SelectionDAG &DAG) const {
@@ -12115,8 +12080,8 @@ SDValue PPCTargetLowering::LowerSSUBO(SDValue Op, SelectionDAG &DAG) const {
1211512080
///
1211612081
SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
1211712082
switch (Op.getOpcode()) {
12118-
default:
12119-
llvm_unreachable("Wasn't expecting to be able to lower this!");
12083+
default: llvm_unreachable("Wasn't expecting to be able to lower this!");
12084+
case ISD::UADDO: return LowerUaddo(Op, DAG);
1212012085
case ISD::FPOW: return lowerPow(Op, DAG);
1212112086
case ISD::FSIN: return lowerSin(Op, DAG);
1212212087
case ISD::FCOS: return lowerCos(Op, DAG);
@@ -12209,12 +12174,6 @@ SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
1220912174
return LowerATOMIC_LOAD_STORE(Op, DAG);
1221012175
case ISD::IS_FPCLASS:
1221112176
return LowerIS_FPCLASS(Op, DAG);
12212-
case ISD::UADDO:
12213-
case ISD::USUBO:
12214-
return LowerADDSUBO(Op, DAG);
12215-
case ISD::UADDO_CARRY:
12216-
case ISD::USUBO_CARRY:
12217-
return LowerADDSUBO_CARRY(Op, DAG);
1221812177
}
1221912178
}
1222012179

@@ -16150,21 +16109,6 @@ static bool isStoreConditional(SDValue Intrin, unsigned &StoreWidth) {
1615016109
return true;
1615116110
}
1615216111

16153-
static SDValue DAGCombineAddc(SDNode *N,
16154-
llvm::PPCTargetLowering::DAGCombinerInfo &DCI) {
16155-
if (N->getOpcode() == PPCISD::ADDC && N->hasAnyUseOfValue(1)) {
16156-
// (ADDC (ADDE 0, 0, C), -1) -> C
16157-
SDValue LHS = N->getOperand(0);
16158-
SDValue RHS = N->getOperand(1);
16159-
if (LHS->getOpcode() == PPCISD::ADDE &&
16160-
isNullConstant(LHS->getOperand(0)) &&
16161-
isNullConstant(LHS->getOperand(1)) && isAllOnesConstant(RHS)) {
16162-
return DCI.CombineTo(N, SDValue(N, 0), LHS->getOperand(2));
16163-
}
16164-
}
16165-
return SDValue();
16166-
}
16167-
1616816112
SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
1616916113
DAGCombinerInfo &DCI) const {
1617016114
SelectionDAG &DAG = DCI.DAG;
@@ -16953,8 +16897,6 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
1695316897
}
1695416898
case ISD::BUILD_VECTOR:
1695516899
return DAGCombineBuildVector(N, DCI);
16956-
case PPCISD::ADDC:
16957-
return DAGCombineAddc(N, DCI);
1695816900
}
1695916901

1696016902
return SDValue();
@@ -17008,16 +16950,6 @@ void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
1700816950
Known.Zero = 0xFFFF0000;
1700916951
break;
1701016952
}
17011-
case PPCISD::ADDE: {
17012-
if (Op.getResNo() == 0) {
17013-
// (0|1), _ = ADDE 0, 0, CARRY
17014-
SDValue LHS = Op.getOperand(0);
17015-
SDValue RHS = Op.getOperand(1);
17016-
if (isNullConstant(LHS) && isNullConstant(RHS))
17017-
Known.Zero = ~1ULL;
17018-
}
17019-
break;
17020-
}
1702116953
case ISD::INTRINSIC_WO_CHAIN: {
1702216954
switch (Op.getConstantOperandVal(0)) {
1702316955
default: break;
@@ -18287,8 +18219,7 @@ static SDValue combineADDToADDZE(SDNode *N, SelectionDAG &DAG,
1828718219
return SDValue();
1828818220

1828918221
SDLoc DL(N);
18290-
EVT CarryType = Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
18291-
SDVTList VTs = DAG.getVTList(MVT::i64, CarryType);
18222+
SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Glue);
1829218223
SDValue Cmp = RHS.getOperand(0);
1829318224
SDValue Z = Cmp.getOperand(0);
1829418225
auto *Constant = cast<ConstantSDNode>(Cmp.getOperand(1));
@@ -18306,14 +18237,11 @@ static SDValue combineADDToADDZE(SDNode *N, SelectionDAG &DAG,
1830618237
SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Z,
1830718238
DAG.getConstant(NegConstant, DL, MVT::i64));
1830818239
SDValue AddOrZ = NegConstant != 0 ? Add : Z;
18309-
SDValue Addc =
18310-
DAG.getNode(ISD::UADDO_CARRY, DL, DAG.getVTList(MVT::i64, CarryType),
18311-
AddOrZ, DAG.getAllOnesConstant(DL, MVT::i64),
18312-
DAG.getConstant(0, DL, CarryType));
18313-
return DAG.getNode(ISD::UADDO_CARRY, DL, VTs, LHS,
18314-
DAG.getConstant(0, DL, MVT::i64),
18240+
SDValue Addc = DAG.getNode(ISD::ADDC, DL, DAG.getVTList(MVT::i64, MVT::Glue),
18241+
AddOrZ, DAG.getAllOnesConstant(DL, MVT::i64));
18242+
return DAG.getNode(ISD::ADDE, DL, VTs, LHS, DAG.getConstant(0, DL, MVT::i64),
1831518243
SDValue(Addc.getNode(), 1));
18316-
}
18244+
}
1831718245
case ISD::SETEQ: {
1831818246
// when C == 0
1831918247
// --> addze X, (subfic Z, 0).carry
@@ -18324,15 +18252,11 @@ static SDValue combineADDToADDZE(SDNode *N, SelectionDAG &DAG,
1832418252
SDValue Add = DAG.getNode(ISD::ADD, DL, MVT::i64, Z,
1832518253
DAG.getConstant(NegConstant, DL, MVT::i64));
1832618254
SDValue AddOrZ = NegConstant != 0 ? Add : Z;
18327-
SDValue Subc =
18328-
DAG.getNode(ISD::USUBO_CARRY, DL, DAG.getVTList(MVT::i64, CarryType),
18329-
DAG.getConstant(0, DL, MVT::i64), AddOrZ,
18330-
DAG.getConstant(0, DL, CarryType));
18331-
SDValue Invert = DAG.getNode(ISD::XOR, DL, CarryType, Subc.getValue(1),
18332-
DAG.getAllOnesConstant(DL, CarryType));
18333-
return DAG.getNode(ISD::UADDO_CARRY, DL, VTs, LHS,
18334-
DAG.getConstant(0, DL, MVT::i64), Invert);
18335-
}
18255+
SDValue Subc = DAG.getNode(ISD::SUBC, DL, DAG.getVTList(MVT::i64, MVT::Glue),
18256+
DAG.getConstant(0, DL, MVT::i64), AddOrZ);
18257+
return DAG.getNode(ISD::ADDE, DL, VTs, LHS, DAG.getConstant(0, DL, MVT::i64),
18258+
SDValue(Subc.getNode(), 1));
18259+
}
1833618260
}
1833718261

1833818262
return SDValue();

‎llvm/lib/Target/PowerPC/PPCISelLowering.h

Lines changed: 1 addition & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -161,12 +161,6 @@ namespace llvm {
161161
SRA,
162162
SHL,
163163

164-
/// These nodes represent PPC arithmetic operations with carry.
165-
ADDC,
166-
ADDE,
167-
SUBC,
168-
SUBE,
169-
170164
/// FNMSUB - Negated multiply-subtract instruction.
171165
FNMSUB,
172166

@@ -1286,6 +1280,7 @@ namespace llvm {
12861280
SDValue LowerGlobalTLSAddressLinux(SDValue Op, SelectionDAG &DAG) const;
12871281
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
12881282
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
1283+
SDValue LowerUaddo(SDValue Op, SelectionDAG &DAG) const;
12891284
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
12901285
SDValue LowerSSUBO(SDValue Op, SelectionDAG &DAG) const;
12911286
SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
@@ -1321,8 +1316,6 @@ namespace llvm {
13211316
SDValue LowerBSWAP(SDValue Op, SelectionDAG &DAG) const;
13221317
SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
13231318
SDValue LowerIS_FPCLASS(SDValue Op, SelectionDAG &DAG) const;
1324-
SDValue LowerADDSUBO_CARRY(SDValue Op, SelectionDAG &DAG) const;
1325-
SDValue LowerADDSUBO(SDValue Op, SelectionDAG &DAG) const;
13261319
SDValue lowerToLibCall(const char *LibCallName, SDValue Op,
13271320
SelectionDAG &DAG) const;
13281321
SDValue lowerLibCallBasedOnType(const char *LibCallFloatName,

‎llvm/lib/Target/PowerPC/PPCInstr64Bit.td

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -760,13 +760,13 @@ def STFDXTLS : XForm_8<31, 727, (outs), (ins f8rc:$RST, ptr_rc_nor0:$RA, tlsreg:
760760
let isCommutable = 1 in
761761
defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
762762
"addc", "$RT, $RA, $RB", IIC_IntGeneral,
763-
[(set i64:$RT, (PPCaddc i64:$RA, i64:$RB))]>,
763+
[(set i64:$RT, (addc i64:$RA, i64:$RB))]>,
764764
PPC970_DGroup_Cracked;
765765

766766
let Defs = [CARRY] in
767767
def ADDIC8 : DForm_2<12, (outs g8rc:$RST), (ins g8rc:$RA, s16imm64:$D),
768768
"addic $RST, $RA, $D", IIC_IntGeneral,
769-
[(set i64:$RST, (PPCaddc i64:$RA, imm64SExt16:$D))]>;
769+
[(set i64:$RST, (addc i64:$RA, imm64SExt16:$D))]>;
770770
def ADDI8 : DForm_2<14, (outs g8rc:$RST), (ins g8rc_nox0:$RA, s16imm64:$D),
771771
"addi $RST, $RA, $D", IIC_IntSimple,
772772
[(set i64:$RST, (add i64:$RA, imm64SExt16:$D))]>;
@@ -782,11 +782,11 @@ def LA8 : DForm_2<14, (outs g8rc:$RST), (ins g8rc_nox0:$RA, s16imm64:$D),
782782
let Defs = [CARRY] in {
783783
def SUBFIC8: DForm_2< 8, (outs g8rc:$RST), (ins g8rc:$RA, s16imm64:$D),
784784
"subfic $RST, $RA, $D", IIC_IntGeneral,
785-
[(set i64:$RST, (PPCsubc imm64SExt16:$D, i64:$RA))]>;
785+
[(set i64:$RST, (subc imm64SExt16:$D, i64:$RA))]>;
786786
}
787787
defm SUBFC8 : XOForm_1rc<31, 8, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
788788
"subfc", "$RT, $RA, $RB", IIC_IntGeneral,
789-
[(set i64:$RT, (PPCsubc i64:$RB, i64:$RA))]>,
789+
[(set i64:$RT, (subc i64:$RB, i64:$RA))]>,
790790
PPC970_DGroup_Cracked;
791791
defm SUBF8 : XOForm_1rx<31, 40, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
792792
"subf", "$RT, $RA, $RB", IIC_IntGeneral,
@@ -798,22 +798,22 @@ let Uses = [CARRY] in {
798798
let isCommutable = 1 in
799799
defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
800800
"adde", "$RT, $RA, $RB", IIC_IntGeneral,
801-
[(set i64:$RT, (PPCadde i64:$RA, i64:$RB, CARRY))]>;
801+
[(set i64:$RT, (adde i64:$RA, i64:$RB))]>;
802802
defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$RT), (ins g8rc:$RA),
803803
"addme", "$RT, $RA", IIC_IntGeneral,
804-
[(set i64:$RT, (PPCadde i64:$RA, -1, CARRY))]>;
804+
[(set i64:$RT, (adde i64:$RA, -1))]>;
805805
defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$RT), (ins g8rc:$RA),
806806
"addze", "$RT, $RA", IIC_IntGeneral,
807-
[(set i64:$RT, (PPCadde i64:$RA, 0, CARRY))]>;
807+
[(set i64:$RT, (adde i64:$RA, 0))]>;
808808
defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$RT), (ins g8rc:$RA, g8rc:$RB),
809809
"subfe", "$RT, $RA, $RB", IIC_IntGeneral,
810-
[(set i64:$RT, (PPCsube i64:$RB, i64:$RA, CARRY))]>;
810+
[(set i64:$RT, (sube i64:$RB, i64:$RA))]>;
811811
defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$RT), (ins g8rc:$RA),
812812
"subfme", "$RT, $RA", IIC_IntGeneral,
813-
[(set i64:$RT, (PPCsube -1, i64:$RA, CARRY))]>;
813+
[(set i64:$RT, (sube -1, i64:$RA))]>;
814814
defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$RT), (ins g8rc:$RA),
815815
"subfze", "$RT, $RA", IIC_IntGeneral,
816-
[(set i64:$RT, (PPCsube 0, i64:$RA, CARRY))]>;
816+
[(set i64:$RT, (sube 0, i64:$RA))]>;
817817
}
818818
} // isCodeGenOnly
819819

‎llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

Lines changed: 0 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -1758,23 +1758,6 @@ void PPCInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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BuildMI(MBB, I, DL, get(PPC::EFDCFS), DestReg).addReg(SrcReg);
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getKillRegState(KillSrc);
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return;
1761-
} else if ((PPC::G8RCRegClass.contains(DestReg) ||
1762-
PPC::GPRCRegClass.contains(DestReg)) &&
1763-
SrcReg == PPC::CARRY) {
1764-
bool Is64Bit = PPC::G8RCRegClass.contains(DestReg);
1765-
BuildMI(MBB, I, DL, get(Is64Bit ? PPC::MFSPR8 : PPC::MFSPR), DestReg)
1766-
.addImm(1)
1767-
.addReg(PPC::CARRY, RegState::Implicit);
1768-
return;
1769-
} else if ((PPC::G8RCRegClass.contains(SrcReg) ||
1770-
PPC::GPRCRegClass.contains(SrcReg)) &&
1771-
DestReg == PPC::CARRY) {
1772-
bool Is64Bit = PPC::G8RCRegClass.contains(SrcReg);
1773-
BuildMI(MBB, I, DL, get(Is64Bit ? PPC::MTSPR8 : PPC::MTSPR))
1774-
.addImm(1)
1775-
.addReg(SrcReg)
1776-
.addReg(PPC::CARRY, RegState::ImplicitDefine);
1777-
return;
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}
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17801763
unsigned Opc;

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