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lld/ELF/Arch/LoongArch.cpp

Lines changed: 7 additions & 1 deletion
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@@ -809,7 +809,13 @@ static void relaxPCHi20Lo12(Ctx &ctx, const InputSection &sec, size_t i,
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// Note: If we can ensure that the .o files generated by LLVM only contain
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// relaxable instruction sequences with R_LARCH_RELAX, then we do not need to
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// check instruction opcodes.
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// decode instructions. The relaxable instruction sequences imply the
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// following constraints:
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// * For relocation pairs related to got_pc, the opcodes of instructions
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// must be pcalau12i + ld.w/d. In other cases, the opcodes must be pcalau12i +
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// addi.w/d.
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// * The destination register of pcalau12i is guaranteed to be used only by
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// the immediately following instruction.
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const uint32_t nextInsn = read32le(sec.content().data() + rLo12.offset);
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sec.relaxAux->relocTypes[i] = R_LARCH_RELAX;

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