Add comments. NFC.

Author: ylzsx

lld/ELF/Arch/LoongArch.cpp

@@ -809,7 +809,13 @@ static void relaxPCHi20Lo12(Ctx &ctx, const InputSection &sec, size_t i,
 
   // Note: If we can ensure that the .o files generated by LLVM only contain
   // relaxable instruction sequences with R_LARCH_RELAX, then we do not need to
-  // check instruction opcodes.
+  // decode instructions. The relaxable instruction sequences imply the
+  // following constraints:
+  // * For relocation pairs related to got_pc, the opcodes of instructions
+  // must be pcalau12i + ld.w/d. In other cases, the opcodes must be pcalau12i +
+  // addi.w/d.
+  // * The destination register of pcalau12i is guaranteed to be used only by
+  // the immediately following instruction.
   const uint32_t nextInsn = read32le(sec.content().data() + rLo12.offset);
 
   sec.relaxAux->relocTypes[i] = R_LARCH_RELAX;