Skip to content

Commit acd6cb8

Browse files
authored
[RISCV][GISel] Support fcmp and fclass for Zfh. (#96696)
1 parent e1015ae commit acd6cb8

15 files changed

+1687
-11
lines changed

llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1148,16 +1148,16 @@ bool RISCVInstructionSelector::selectSelect(MachineInstr &MI,
11481148

11491149
// Convert an FCMP predicate to one of the supported F or D instructions.
11501150
static unsigned getFCmpOpcode(CmpInst::Predicate Pred, unsigned Size) {
1151-
assert((Size == 32 || Size == 64) && "Unsupported size");
1151+
assert((Size == 16 || Size == 32 || Size == 64) && "Unsupported size");
11521152
switch (Pred) {
11531153
default:
11541154
llvm_unreachable("Unsupported predicate");
11551155
case CmpInst::FCMP_OLT:
1156-
return Size == 32 ? RISCV::FLT_S : RISCV::FLT_D;
1156+
return Size == 16 ? RISCV::FLT_H : Size == 32 ? RISCV::FLT_S : RISCV::FLT_D;
11571157
case CmpInst::FCMP_OLE:
1158-
return Size == 32 ? RISCV::FLE_S : RISCV::FLE_D;
1158+
return Size == 16 ? RISCV::FLE_H : Size == 32 ? RISCV::FLE_S : RISCV::FLE_D;
11591159
case CmpInst::FCMP_OEQ:
1160-
return Size == 32 ? RISCV::FEQ_S : RISCV::FEQ_D;
1160+
return Size == 16 ? RISCV::FEQ_H : Size == 32 ? RISCV::FEQ_S : RISCV::FEQ_D;
11611161
}
11621162
}
11631163

@@ -1209,7 +1209,7 @@ bool RISCVInstructionSelector::selectFPCompare(MachineInstr &MI,
12091209
Register RHS = CmpMI.getRHSReg();
12101210

12111211
unsigned Size = MRI.getType(LHS).getSizeInBits();
1212-
assert((Size == 32 || Size == 64) && "Unexpected size");
1212+
assert((Size == 16 || Size == 32 || Size == 64) && "Unexpected size");
12131213

12141214
Register TmpReg = DstReg;
12151215

llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

Lines changed: 12 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -402,13 +402,20 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
402402
typeIs(1, s32)(Query));
403403
});
404404

405-
getActionDefinitionsBuilder(G_FCMP)
406-
.legalIf(all(typeIs(0, sXLen), typeIsScalarFPArith(1, ST)))
407-
.clampScalar(0, sXLen, sXLen);
405+
auto &FCmpActions = getActionDefinitionsBuilder(G_FCMP).legalIf(
406+
all(typeIs(0, sXLen), typeIsScalarFPArith(1, ST)));
407+
// TODO: Fold this into typeIsScalarFPArith.
408+
if (ST.hasStdExtZfh())
409+
FCmpActions.legalFor({sXLen, s16});
410+
FCmpActions.clampScalar(0, sXLen, sXLen);
408411

409412
// TODO: Support vector version of G_IS_FPCLASS.
410-
getActionDefinitionsBuilder(G_IS_FPCLASS)
411-
.customIf(all(typeIs(0, s1), typeIsScalarFPArith(1, ST)));
413+
auto &FClassActions =
414+
getActionDefinitionsBuilder(G_IS_FPCLASS)
415+
.customIf(all(typeIs(0, s1), typeIsScalarFPArith(1, ST)));
416+
// TODO: Fold this into typeIsScalarFPArith.
417+
if (ST.hasStdExtZfh())
418+
FClassActions.customFor({s1, s16});
412419

413420
auto &FConstantActions = getActionDefinitionsBuilder(G_FCONSTANT)
414421
.legalIf(typeIsScalarFPArith(0, ST));

llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -478,7 +478,6 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
478478
LLT Ty = MRI.getType(MI.getOperand(2).getReg());
479479

480480
unsigned Size = Ty.getSizeInBits();
481-
assert((Size == 32 || Size == 64) && "Unsupported size for G_FCMP");
482481

483482
OpdsMapping[0] = GPRValueMapping;
484483
OpdsMapping[2] = OpdsMapping[3] = getFPValueMapping(Size);

0 commit comments

Comments
 (0)