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1 parent 2ec697b commit ad762f2Copy full SHA for ad762f2
llvm/test/CodeGen/X86/pr39098.ll
@@ -1,13 +1,15 @@
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+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
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define dso_local void @test_cancel2(ptr %p1, ptr %p2) {
-; CHECK: # %entry
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-; CHECK-NEXT: movl (%rdi), %eax
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-; CHECK-NEXT: shrl %eax
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-; CHECK-NEXT: andl $524287, %eax
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-; CHECK-NEXT: movl %eax, (%rsi)
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-; CHECK-NEXT: movb $0, 4(%rsi)
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-; CHECK-NEXT: retq
+; CHECK-LABEL: test_cancel2:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movl (%rdi), %eax
+; CHECK-NEXT: shrl %eax
+; CHECK-NEXT: andl $524287, %eax # imm = 0x7FFFF
+; CHECK-NEXT: movl %eax, (%rsi)
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+; CHECK-NEXT: movb $0, 4(%rsi)
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+; CHECK-NEXT: retq
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entry:
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%0 = load i40, ptr %p1, align 8
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%shl414 = shl i40 %0, 19
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