@@ -151,18 +151,6 @@ class SPIRVInstructionSelector : public InstructionSelector {
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bool selectFCmp (Register ResVReg, const SPIRVType *ResType ,
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MachineInstr &I) const ;
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- bool selectFmix (Register ResVReg, const SPIRVType *ResType ,
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- MachineInstr &I) const ;
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-
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- bool selectLength (Register ResVReg, const SPIRVType *ResType ,
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- MachineInstr &I) const ;
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-
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- bool selectFrac (Register ResVReg, const SPIRVType *ResType ,
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- MachineInstr &I) const ;
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-
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- bool selectRsqrt (Register ResVReg, const SPIRVType *ResType ,
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- MachineInstr &I) const ;
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-
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bool selectSign (Register ResVReg, const SPIRVType *ResType ,
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MachineInstr &I) const ;
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@@ -235,18 +223,12 @@ class SPIRVInstructionSelector : public InstructionSelector {
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bool selectLog10 (Register ResVReg, const SPIRVType *ResType ,
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MachineInstr &I) const ;
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- bool selectNormalize (Register ResVReg, const SPIRVType *ResType ,
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- MachineInstr &I) const ;
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-
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bool selectSaturate (Register ResVReg, const SPIRVType *ResType ,
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MachineInstr &I) const ;
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bool selectSpvThreadId (Register ResVReg, const SPIRVType *ResType ,
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MachineInstr &I) const ;
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- bool selectStep (Register ResVReg, const SPIRVType *ResType ,
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- MachineInstr &I) const ;
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-
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bool selectUnmergeValues (MachineInstr &I) const ;
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// Utilities
@@ -802,8 +784,13 @@ bool SPIRVInstructionSelector::selectExtInst(Register ResVReg,
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.addImm (static_cast <uint32_t >(Set))
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.addImm (Opcode);
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const unsigned NumOps = I.getNumOperands ();
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- for (unsigned i = 1 ; i < NumOps; ++i)
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- MIB.add (I.getOperand (i));
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+ unsigned Index = 1 ;
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+ if (Index < NumOps &&
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+ I.getOperand (Index).getType () ==
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+ MachineOperand::MachineOperandType::MO_IntrinsicID)
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+ Index = 2 ;
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+ for (; Index < NumOps; ++Index)
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+ MIB.add (I.getOperand (Index));
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return MIB.constrainAllUses (TII, TRI, RBI);
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}
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}
@@ -1605,95 +1592,6 @@ bool SPIRVInstructionSelector::selectAny(Register ResVReg,
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return selectAnyOrAll (ResVReg, ResType , I, SPIRV::OpAny);
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}
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- bool SPIRVInstructionSelector::selectFmix (Register ResVReg,
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- const SPIRVType *ResType ,
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- MachineInstr &I) const {
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-
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- assert (I.getNumOperands () == 5 );
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- assert (I.getOperand (2 ).isReg ());
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- assert (I.getOperand (3 ).isReg ());
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- assert (I.getOperand (4 ).isReg ());
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- MachineBasicBlock &BB = *I.getParent ();
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-
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- return BuildMI (BB, I, I.getDebugLoc (), TII.get (SPIRV::OpExtInst))
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- .addDef (ResVReg)
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- .addUse (GR.getSPIRVTypeID (ResType ))
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- .addImm (static_cast <uint32_t >(SPIRV::InstructionSet::GLSL_std_450))
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- .addImm (GL::FMix)
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- .addUse (I.getOperand (2 ).getReg ())
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- .addUse (I.getOperand (3 ).getReg ())
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- .addUse (I.getOperand (4 ).getReg ())
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- .constrainAllUses (TII, TRI, RBI);
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- }
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-
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- bool SPIRVInstructionSelector::selectLength (Register ResVReg,
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- const SPIRVType *ResType ,
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- MachineInstr &I) const {
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-
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- assert (I.getNumOperands () == 3 );
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- assert (I.getOperand (2 ).isReg ());
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- MachineBasicBlock &BB = *I.getParent ();
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-
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- return BuildMI (BB, I, I.getDebugLoc (), TII.get (SPIRV::OpExtInst))
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- .addDef (ResVReg)
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- .addUse (GR.getSPIRVTypeID (ResType ))
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- .addImm (static_cast <uint32_t >(SPIRV::InstructionSet::GLSL_std_450))
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- .addImm (GL::Length)
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- .addUse (I.getOperand (2 ).getReg ())
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- .constrainAllUses (TII, TRI, RBI);
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- }
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-
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- bool SPIRVInstructionSelector::selectFrac (Register ResVReg,
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- const SPIRVType *ResType ,
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- MachineInstr &I) const {
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-
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- assert (I.getNumOperands () == 3 );
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- assert (I.getOperand (2 ).isReg ());
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- MachineBasicBlock &BB = *I.getParent ();
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-
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- return BuildMI (BB, I, I.getDebugLoc (), TII.get (SPIRV::OpExtInst))
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- .addDef (ResVReg)
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- .addUse (GR.getSPIRVTypeID (ResType ))
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- .addImm (static_cast <uint32_t >(SPIRV::InstructionSet::GLSL_std_450))
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- .addImm (GL::Fract )
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- .addUse (I.getOperand (2 ).getReg ())
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- .constrainAllUses (TII, TRI, RBI);
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- }
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-
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- bool SPIRVInstructionSelector::selectNormalize (Register ResVReg,
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- const SPIRVType *ResType ,
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- MachineInstr &I) const {
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-
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- assert (I.getNumOperands () == 3 );
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- assert (I.getOperand (2 ).isReg ());
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- MachineBasicBlock &BB = *I.getParent ();
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-
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- return BuildMI (BB, I, I.getDebugLoc (), TII.get (SPIRV::OpExtInst))
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- .addDef (ResVReg)
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- .addUse (GR.getSPIRVTypeID (ResType ))
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- .addImm (static_cast <uint32_t >(SPIRV::InstructionSet::GLSL_std_450))
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- .addImm (GL::Normalize)
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- .addUse (I.getOperand (2 ).getReg ())
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- .constrainAllUses (TII, TRI, RBI);
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- }
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-
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- bool SPIRVInstructionSelector::selectRsqrt (Register ResVReg,
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- const SPIRVType *ResType ,
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- MachineInstr &I) const {
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-
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- assert (I.getNumOperands () == 3 );
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- assert (I.getOperand (2 ).isReg ());
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- MachineBasicBlock &BB = *I.getParent ();
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-
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- return BuildMI (BB, I, I.getDebugLoc (), TII.get (SPIRV::OpExtInst))
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- .addDef (ResVReg)
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- .addUse (GR.getSPIRVTypeID (ResType ))
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- .addImm (static_cast <uint32_t >(SPIRV::InstructionSet::GLSL_std_450))
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- .addImm (GL::InverseSqrt)
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- .addUse (I.getOperand (2 ).getReg ())
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- .constrainAllUses (TII, TRI, RBI);
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- }
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-
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// Select the OpDot instruction for the given float dot
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bool SPIRVInstructionSelector::selectFloatDot (Register ResVReg,
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const SPIRVType *ResType ,
@@ -1853,25 +1751,6 @@ bool SPIRVInstructionSelector::selectSign(Register ResVReg,
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return Result;
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}
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- bool SPIRVInstructionSelector::selectStep (Register ResVReg,
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- const SPIRVType *ResType ,
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- MachineInstr &I) const {
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-
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- assert (I.getNumOperands () == 4 );
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- assert (I.getOperand (2 ).isReg ());
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- assert (I.getOperand (3 ).isReg ());
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- MachineBasicBlock &BB = *I.getParent ();
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-
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- return BuildMI (BB, I, I.getDebugLoc (), TII.get (SPIRV::OpExtInst))
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- .addDef (ResVReg)
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- .addUse (GR.getSPIRVTypeID (ResType ))
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- .addImm (static_cast <uint32_t >(SPIRV::InstructionSet::GLSL_std_450))
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- .addImm (GL::Step)
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- .addUse (I.getOperand (2 ).getReg ())
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- .addUse (I.getOperand (3 ).getReg ())
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- .constrainAllUses (TII, TRI, RBI);
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- }
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-
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bool SPIRVInstructionSelector::selectBitreverse (Register ResVReg,
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const SPIRVType *ResType ,
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MachineInstr &I) const {
@@ -2622,15 +2501,15 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
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case Intrinsic::spv_any:
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return selectAny (ResVReg, ResType , I);
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case Intrinsic::spv_lerp:
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- return selectFmix (ResVReg, ResType , I);
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+ return selectExtInst (ResVReg, ResType , I, CL::mix, GL::FMix );
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case Intrinsic::spv_length:
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- return selectLength (ResVReg, ResType , I);
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+ return selectExtInst (ResVReg, ResType , I, CL::length, GL::Length );
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case Intrinsic::spv_frac:
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- return selectFrac (ResVReg, ResType , I);
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+ return selectExtInst (ResVReg, ResType , I, CL::fract, GL:: Fract );
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case Intrinsic::spv_normalize:
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- return selectNormalize (ResVReg, ResType , I);
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+ return selectExtInst (ResVReg, ResType , I, CL::normalize, GL::Normalize );
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case Intrinsic::spv_rsqrt:
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- return selectRsqrt (ResVReg, ResType , I);
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+ return selectExtInst (ResVReg, ResType , I, CL::rsqrt, GL::InverseSqrt );
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case Intrinsic::spv_sign:
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return selectSign (ResVReg, ResType , I);
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case Intrinsic::spv_lifetime_start:
@@ -2654,7 +2533,7 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg,
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.addUse (GR.getOrCreateConstInt (3 , I, IntTy, TII));
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}
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case Intrinsic::spv_step:
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- return selectStep (ResVReg, ResType , I);
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+ return selectExtInst (ResVReg, ResType , I, CL::step, GL::Step );
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// Discard intrinsics which we do not expect to actually represent code after
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// lowering or intrinsics which are not implemented but should not crash when
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// found in a customer's LLVM IR input.
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